Method of testing electronic circuits and corresponding circuit
AssigneeSTMicroelectronics S.r.l.
InventorDavid Vincenzoni
Life of this patent
Estimating the term…
Abstract
A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.
Claims23
A method of testing an electronic circuit configured to produce a sequence of N-bit digital data at an output port as a result of signals applied to an input node, the method comprising:
- applying a test stimulus signal to the input node;
- collecting a sequence of N-bit digital test data at the output port, the N-bit digital test data determined by the test stimulus signal applied to the input node;
- applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data, wherein R is less than N;
- and
- making the R-bit compressed test data available in parallel format over R output pins of the electronic circuit.
A method of testing an electronic circuit, the method comprising:
- applying a test stimulus signal to an input node of the electronic circuit;
- receiving R-bit compressed test data from R output pins of the electronic circuit, where R is a real number;
- reconstructing N-bit digital test data from the R-bit compressed test data, wherein N is a real number greater than R;
- and
- performing the testing on the N-bit digital test data that was reconstructed from the R-bit compressed test data.
A first circuit comprising:
- a second circuit configured to produce a sequence of N-bit digital test data at an output port of the second circuit in response to a stimulus signal applied to an input node of the second circuit;
- compression circuitry coupled to the output port of the second circuit, the compression circuitry configured to apply N-bit to R-bit lossless compression to N-bit digital test data at the output port to obtain therefrom R-bit compressed test data, wherein R is less than N;
- and
- a plurality of R output pins coupled to the compression circuitry to receive therefrom the R-bit compressed test data in parallel format.
Dependencies are inferred from the claim text.