Pipeline analog to digital converter and timing adjustment method

A timing adjustment method, comprising:

• providing a first clock signal to one of a plurality of converter circuitries in a pipeline analog to digital converter, wherein the one of the plurality of converter circuitries is configured to perform a quantization according to a first signal to generate a digital code, and process the digital code and the first signal to generate a current stage residue signal;
• detecting whether the quantization is complete, in order to generate a control signal;
• storing information that indicates a maximum delay time of the first clock signal to a memory circuit;
• obtaining the control signal from the memory circuit according to the information;
• and
• adjusting a timing of the first clock signal according to the control signal.

A pipeline analog to digital converter, comprising:

• a plurality of converter circuitries, configured to sequentially convert an input signal to be a plurality of digital codes, wherein one of the plurality of converter circuitries comprises:
• a sub-analog to digital converter circuit configured to perform a quantization according to a first signal to generate a corresponding one of the plurality of digital codes, wherein the first signal is the input signal or a previous stage residue signal;
• and
• a multiplying digital to analog converter circuit configured to process the corresponding one of the plurality of digital codes in response to a first clock signal, in order to generate a current stage residue signal;
• a detector circuitry configured to detect whether the quantization is complete, in order to generate a control signal;
• and
• a clock generator circuit configured to adjust a timing of the first clock signal according to the control signal,
• wherein when the detector circuitry detects that the quantization is not complete, the clock generator circuit is configured to delay a transiting edge of the first clock signal according to the control signal, such that a timing for the multiplying digital to analog converter circuit to process the corresponding one of the plurality of digital codes and the first signal is delayed.