Systems and methods for energy-efficient analog matrix multiplication for machine learning processes
AssigneeMaxim Integrated Products, Inc.
InventorsSung Ung Kwak, Robert Michael Muchsel
Life of this patent
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Abstract
A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.
Claims20
A matrix multiplication system comprising:
- a first sub-circuit associated with a first column weight, the first sub-circuit comprising:
- a data memory;
- a magnitude adjustment circuit that adjusts magnitudes of values obtained from the data memory to generate magnitude-adjusted values;
- and
- a multiplier coupled to the first column weight, the multiplier multiples the magnitude-adjusted values with the first column weight to obtain a partial product;
- an adder coupled to a set of sub-circuits comprising the first sub-circuit, the adder adds the outputs of one or more multipliers to obtain a sum of partial products;
- and
- an activation unit coupled to the adder, the activation unit applies an activation function to the sum of partial products to generate a matrix multiplication result.
A method for performing an analog matrix multiplication, the method comprising:
- using an analog multiplication circuit to multiply a first bit of a data item with a first weight to obtain a first product that corresponds to a first set of currents;
- multiplying a second bit of the data item with a second weight to obtain a second product that corresponds to a second set of currents;
- adding the first and second set of currents to obtain an output current that represents a sum of partial dot products in a matrix multiplication;
- weighing the output current according to a bit position;
- converting the output current into a digital format to obtain a digitized result;
- and
- applying an activation function to the digitized result to generate a matrix multiplication result.
An analog multiplication circuit comprising:
- a first set of switches that represents a set of weight bits for currents flowing through the first set of switches;
- and
- a second set of switches that represents a set of data bits for currents flowing through the second set of switches, the analog multiplication circuit performs steps comprising:
- multiplying a first data bit from the set of data bits with a first weight bit from the set of weight bits to obtain a first product that corresponds to a first set of currents;
- multiplying a second data bit from the set of data bits with a second weight bit from the set of weight bits to obtain a second product that corresponds to a second set of currents;
- and
- adding, in the analog domain, at least some of the currents flowing through the first set of switches and the second set of switches to obtain an output current that represents a sum of partial dot products in a matrix-multiplication.
Dependencies are inferred from the claim text.