# US 11,490,519 B2 · Printed stacked micro-devices

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- Number: US 11,490,519 B2
- Document ID: US11490519B2
- Status: Granted
- Kind: B2
- Application number: 17/146,295
- Filed: 2021-01-11
- Published: 2022-07-14
- Granted: 2022-11-01
- Earliest claimed: 2021-01-11
- Assignees: X-Celeprint Limited
- Applicants: X-Celeprint Limited
- Inventors: Ronald S. Cok
- Web page: https://patentgrep.com/patent/US11490519B2

## CPC

- H05K 1/182: associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K 1/0243: {Printed circuits associated with mounted high frequency components}
- H05K 1/0284: {Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014)}
- H05K 1/11: Printed elements for providing electric connections to or between printed circuits
- H05K 1/162: {incorporating printed capacitors}
- H05K 1/165: {incorporating printed inductors}
- H05K 1/167: {incorporating printed resistors}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H05K 2201/09263: Meander
- H05K 2201/09763: Printed component having superposed conductors, but integrated in one circuit layer
- H10W 44/248: {for antennas}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/732: {between stacked chips}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stacked electronic component comprises a stack of three or more print layers. Each print layer has an area less than any print layers beneath the print layer in the stack. Each print layer comprises a dielectric layer and a functional layer disposed on the dielectric layer. The functional layer comprises an exposed conductive portion that is not covered with a dielectric layer of any of the print layers and each exposed conductive portion is nonoverlapping with any other exposed conductive portion. A patterned electrode layer is coated on at least a portion of the stack and defines one or more electrodes. Each electrode of the one or more electrodes in electrical contact with an exclusive subset of the exposed conductive portions. The functional layers can be passive conductors forming capacitors, resistors, inductors, or antennas, or active layers forming electronic circuits.

## Claims

### Claim 1

A stacked electronic component, comprising:
a stack of three or more print layers, each print layer in the stack of three or more print layers having an area less than any of the print layers that are beneath the print layer in the stack, wherein each of the print layers comprises a dielectric layer and a functional layer disposed on the dielectric layer, the functional layer comprises an exposed conductive portion that is not covered with a dielectric layer of any of the print layers, and wherein the exposed conductive portion of each of the print layers is nonoverlapping with the exposed conductive portion of any other of the print layers; and
a patterned electrode layer coated on at least a portion of the stack, the patterned electrode layer defining one or more electrodes, each electrode of the one or more electrodes in electrical contact with the exposed conductive portion of each of an exclusive subset of the print layers,
wherein the print layers are mutually non-native to each other, and each print layer comprises a broken or separated print tether.

### Claim 2 (depends on 1)

The stacked electronic component of claim 1, wherein the stacked electronic component is a passive electronic component.

### Claim 3 (depends on 1)

The stacked electronic component of claim 1, wherein the stacked electronic component is an active electronic component.

### Claim 4 (depends on 1)

The stacked electronic component of claim 1, wherein the functional layer (i) is exclusively an electrical conductor, (ii) exclusively a resistive electrical conductor, (iii) comprises an epitaxial layer, or (iv) is an active circuit.

### Claim 5 (depends on 1)

The stacked electronic component of claim 1, wherein the stacked electronic component is a capacitor, a resistor, an inductor, or an antenna.

### Claim 6 (depends on 1)

The stacked electronic component of claim 1, wherein the print layer of each of the stack of three or more print layers is electrically connected exclusively by the patterned electrode layer.

### Claim 7 (depends on 1)

The stacked electronic component of claim 1, wherein the print layer of each of the stack of three or more print layers is adhered to an adjacent print layer with a layer of adhesive.

### Claim 8 (depends on 7)

The stacked electronic component of claim 7, wherein the dielectric layer is the layer of adhesive.

### Claim 9 (depends on 1)

The stacked electronic component of claim 1, wherein the dielectric layer is a bottom dielectric layer and wherein each print layer of the stack of three or more print layers comprises a top dielectric layer disposed on the functional layer on a side of the functional layer opposite the bottom dielectric layer, the top dielectric layer covering the functional layer except for the exposed conductive portion.

### Claim 10 (depends on 9)

The stacked electronic component of claim 9, wherein the top dielectric layer is a layer of adhesive that adheres adjacent print layers of the stack of three or more print layers together.

### Claim 11 (depends on 1)

The stacked electronic component of claim 1, wherein (i) the patterned electrode layer defines only two electrodes, (ii) the one or more electrodes electrically connect fewer than all of the exposed conductive portions, or (iii) both (i) and (ii).

### Claim 12 (depends on 1)

The stacked electronic component of claim 1, wherein the exposed conductive portions of at least two print layers of the stack of three or more print layers are electrically connected by one or more functional-layer connectors that are spatially and physically separate from the one or more electrodes.

### Claim 13 (depends on 12)

The stacked electronic component of claim 12, wherein the one or more functional-layer connectors are disposed in a common layer or wherein the one or more functional-layer connectors are disposed in a common layer with the one or more electrodes.

### Claim 14 (depends on 12)

The stacked electronic component of claim 12, wherein the one or more functional-layer connectors electrically connect the functional layers in series or wherein the one or more functional-layer connectors electrically connect the exposed conductive portions of adjacent print layers of the stack of three or more print layers.

### Claim 15 (depends on 1)

The stacked electronic component of claim 1, wherein the print layers of the stack of three or more print layers are shaped as a polygon and (i) all of the exposed conductive portions of the print layers are disposed on opposing sides of the polygon, (ii) each of the exposed conductive portions of the print layers is disposed on three sides of the polygon, (iii) each of the exposed conductive portions of the print layers is disposed on one side of the polygon, or (iv) all of the exposed conductive portions of the print layers are disposed on one side of the polygon.

### Claim 16 (depends on 1)

The stacked electronic component of claim 1, wherein the dielectric layer has a rectangular shape with an extended tab and the exposed conductive portion is disposed on the tab.

### Claim 17 (depends on 1)

The stacked electronic component of claim 1, wherein none of the exposed conductive portions electrically connected to a first electrode of the one or more electrodes are disposed spatially between the exposed conductive portions electrically connected to a second electrode of the one or more electrodes different from the first electrode in a direction orthogonal to the stack.

### Claim 18 (depends on 1)

The stacked electronic component of claim 1, wherein each functional layer in the stack is a passive electrical conductor that is a plate, a serpentine conductor, or a conductor within and close to at least most of a perimeter of a polygon.

### Claim 19 (depends on 1)

The stacked electronic component of claim 1, comprising an insulating layer disposed over the stack of three or more print layers and vias formed in the insulating layer, wherein the one or more electrodes are electrically connected to the exposed conductive portions through the vias.

### Claim 20 (depends on 1)

The stacked electronic component of claim 1, comprising an alignment structure, wherein the print layers of the stack of three or more print layers are one or more of adjacent to, aligned by, and in contact with the alignment structure.

### Claim 21 (depends on 20)

The stacked electronic component of claim 20, wherein the alignment structure aligns the stack in two dimensions.

### Claim 22 (depends on 1)

The stacked electronic component of claim 1, wherein the functional layer of one or more print layers of the stack of three or more print layers is a vertical capacitor layer.

### Claim 23 (depends on 1)

The stacked electronic component of claim 1, comprising a component substrate comprising a component print layer, the component print layer comprising a component dielectric layer and a component functional layer disposed on the component dielectric layer, the component functional layer comprising a component substrate exposed conductive portion that is not covered with a dielectric layer of any of the print layers, and an electrode of the one or more electrodes is in electrical contact with the component substrate exposed conductive portion.