Condition code anticipator for hexadecimal floating point
AssigneeInternational Business Machines Corporation
InventorsSilvia Melitta Mueller, Petra Leber, Kerstin Claudia Schelm, Cedric Lichtenau
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Abstract
An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.
Claims20
A computer-implemented method comprising:
- executing, by a binary based floating-point arithmetic unit of a processor, a calculation comprising two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction;
- and
- providing, by the floating-point arithmetic unit, a condition code for a calculation result of the calculation,
- wherein the floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result, and
- wherein the condition code anticipator circuit detects a zero result in at least one case where the calculation result is mathematically non-zero when the calculation result is unnormalized and zero when the calculation result is normalized.
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a system comprising one or more processors to cause the system to perform a method comprising:
- executing, by a binary based floating-point arithmetic unit of a processor of the system, a calculation comprising two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction;
- and
- providing, by the floating-point arithmetic unit, a condition code for a calculation result of the calculation,
- wherein the floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result, and
- wherein the condition code anticipator circuit detects a zero result in at least one case where the calculation result is mathematically non-zero when the calculation result is unnormalized and zero when the calculation result is normalized.
A system comprising a binary based floating-point arithmetic unit and one or more processors configured to perform a method comprising:
- executing, by the binary based floating-point arithmetic unit, a calculation comprising two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction;
- and
- providing, by the floating-point arithmetic unit, a condition code for a calculation result of the calculation,
- wherein the floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to a processor prior to availability of the calculation result, and
- wherein the condition code anticipator circuit detects a zero result in at least one case where the calculation result is mathematically non-zero when the calculation result is unnormalized and zero when the calculation result is normalized.
Dependencies are inferred from the claim text.