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US 11,487,464 B2Granted
Neural network memory
AssigneeMicron Technology, Inc.
InventorsMattia Boniardi, Innocenzo Tortorelli
Life of this patent
Estimating the term…
Abstract
An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
Claims20
An apparatus, comprising:
- a memory array comprising:
- a first portion comprising a first plurality of variable resistance memory cells;
- and
- a second portion comprising a second plurality of variable resistance memory cells that have been degraded through forced write cycling;
- and
- a memory controller coupled to the first portion and the second portion, wherein the memory controller is configured to:
- operate the first portion for short-term memory operations;
- and
- operate the second portion for long-term memory operations;
- and
- perform the forced write cycling on the second plurality of variable resistance memory cells prior to operating the second portion.
8 more elements
An apparatus, comprising:
- a memory array comprising:
- a first portion comprising a first plurality of variable resistance memory cells;
- and
- a second portion comprising a second plurality of variable resistance memory cells that have been degraded;
- and
- a memory controller coupled to the memory array, wherein the memory controller is configured to:
- operate the first portion for short-term memory operations;
- operate the second portion for long-term memory operations;
- and
- reclassify a particular one of the first plurality of variable resistance memory cells as one of the second plurality of variable resistance memory cells in response to an operating criterion being met.
7 more elements
A method, comprising:
- performing a first plurality of neural network operations on a plurality of short-term memory cells of a memory array;
- performing a second plurality of neural network operations on a plurality of long-term memory cells of the memory array, and
- transferring data stored in at least one of the plurality of short-term memory cells to be stored in at least one of the plurality of long-term memory cells;
- wherein the data represents a synaptic weight with respect to the first plurality of neural network operations;
- and
- wherein transferring the data comprises transferring the data in response to the first plurality of neural network operations indicating that long-term learning has occurred.
3 more elements
A method, comprising:
- operating a first portion of an array of variable resistance memory cells as short-term memory cells for neural network operations;
- and
- operating a second portion of the array as long-term memory for the neural network operations;
- wherein operating the first portion of the array comprises increasing a conductance of a first one of the variable resistance memory cells between a RESET state and a SET state to represent an increased synaptic weight for short-term memory with respect to the neural network operations;
- wherein operating the second portion of the array comprises increasing a conductance of a second one of the plurality of variable resistance memory cells between a degraded RESET state and a degraded SET state to represent an increased synaptic weight for long-term memory with respect to the neural network operations;
- wherein the degraded RESET state has a greater conductance than the RESET state;
- and
- wherein the degraded SET state has a greater conductance than the SET state.
5 more elements
An apparatus, comprising:
- a memory array comprising:
- a first portion comprising a first plurality of variable resistance memory cells;
- and
- a second portion comprising a second plurality of variable resistance memory cells that have been degraded through forced write cycling;
- and
- a memory controller coupled to the first portion and the second portion, wherein the memory controller is configured to:
- operate the first portion for short-term memory operations by applying a pulse to increase a conductance of any of the first plurality of memory cells while in a RESET state and without transitioning to a SET state;
- wherein increasing the conductance represents an increase to a short-term synaptic weight;
- and
- operate the second portion for long-term memory operations;
- wherein increasing the conductance represents an increase to a short-term synaptic weight.
8 more elements
Dependencies are inferred from the claim text.