Method of making ohmic contact on low doped bulk silicon for optical alignment
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuei-Sung Chang, Chia-Hua Chu, Shang-Ying Tsai
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Abstract
Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) structure including an epitaxial layer overlying a MEMS substrate. The MEMS substrate comprises a moveable element arranged over a carrier substrate. The epitaxial layer has a higher doping concentration than the MEMS substrate. A plurality of contacts overlies the epitaxial layer. A first subset of the plurality of contacts overlies the moveable element. The plurality of contacts respectively has an ohmic contact with the epitaxial layer.
Claims20
A microelectromechanical systems (MEMS) structure comprising:
- a MEMS substrate with a moveable element arranged over a carrier substrate;
- an epitaxial layer overlying the MEMS substrate, wherein the epitaxial layer has a higher doping concentration than the MEMS substrate;
- and
- a plurality of contacts overlying the epitaxial layer, wherein a first subset of the plurality of contacts overlies the moveable element, wherein the plurality of contacts respectively has an ohmic contact with the epitaxial layer.
An integrated chip comprising:
- a dielectric layer overlying a first substrate;
- a second substrate overlying the dielectric layer, wherein a cavity is disposed within the first and second substrates, wherein the second substrate comprises monocrystalline silicon, wherein the second substrate comprises a moveable element disposed within the cavity;
- a plurality of alignment marks overlying the first substrate;
- an epitaxial layer overlying the second substrate, wherein a resistance of the epitaxial layer is less than a resistance of the second substrate;
- and
- a plurality of conductive structures overlying the epitaxial layer, wherein the conductive structures are respectively laterally offset from the alignment marks by one or more non-zero distances.
An integrated chip comprising:
- a first substrate comprising a plurality of alignment marks;
- a second substrate disposed along the first substrate, wherein the first and second substrates respectively comprise monocrystalline silicon, wherein the second substrate comprises a moveable element;
- an epitaxial layer disposed along the second substrate, wherein the epitaxial layer has a higher doping concentration than the first substrate and the second substrate, wherein a cavity is defined between an upper surface of the first substrate and a top surface of the epitaxial layer, wherein the epitaxial layer directly overlies the moveable element, and wherein the moveable element is disposed within the cavity;
- and
- a plurality of conductive contacts disposed along the top surface of the epitaxial layer, wherein the conductive contacts respectively have an ohmic contact with the epitaxial layer, wherein at least one of the plurality of conductive contacts directly overlies the moveable element, and wherein the plurality of conductive contacts is laterally offset from the plurality of alignment marks.
Dependencies are inferred from the claim text.