Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

An apparatus comprising:

• a node;
• a capacitor comprising non-linear polar material, the capacitor having a first terminal coupled to the node and a second terminal coupled to a plate-line, wherein the capacitor is a planar capacitor;
• a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line;
• a refresh circuitry to refresh charge on the capacitor periodically;
• and
• one or more circuitries to boost the word-line above a voltage supply level during a write operation and a read operation, wherein the one or more circuitries is to generate a first pulse on the bit-line after the word-line is boosted and before an end of the boost on the word-line during a first write operation, and wherein the one or more circuitries is to generate a second pulse on the plate-line after the word-line is boosted and before the end of the boost on the word-line during a second write operation different from the first write operation.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a memory to store the one or more instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
• a node;
• a capacitor comprising non-linear polar material, the capacitor having a first terminal coupled to the node and a second terminal coupled to a plate-line, wherein the capacitor is a pillar capacitor;
• a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line;
• a refresh circuitry to refresh charge on the capacitor periodically;
• and
• one or more circuitries to boost the word-line above a voltage supply level during a write operation and a read operation, wherein the one or more circuitries is to generate a first pulse on the bit-line after the word-line is boosted and before an end of the boost on the word-line during a first write operation, and wherein the one or more circuitries is to generate a second pulse on the plate-line after the word-line is boosted and before the end of the boost on the word-line during a second write operation different from the first write operation.