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US 11,481,127 B2Granted
Cryogenic transmitter and semiconductor memory device including the same
AssigneeSK hynix Inc.
InventorKang-Sub Kwak
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.
Claims26
A semiconductor memory device comprising:
- a memory region from which first data and second data are sequentially read;
- and
- a data output circuit including a storage circuit, a control circuit, and an input data control circuit, the data output circuit being suitable for selectively performing a reset operation on a data pad during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad,
- wherein the storage circuit is suitable for storing the first data and outputting the stored first data as third data when the second data is read,
- wherein the control circuit is suitable for generating a reset control signal and an input data control signal based on the first data and the second data;
- wherein the control circuit determines whether to activate the input data control signal according to the first data during the first output enable period,
- wherein the control circuit deactivates the input data control signal regardless of the second data during the second output enable period when a logic level of the second data is equal to a logic level of the third data, and determines whether to activate the input data control signal according to the second data during the second output enable period when the logic level of the second data is different from the logic level of the third data, and
- wherein the control circuit deactivates the input data control circuit during the output disable period.
5 more elements
A semiconductor memory device comprising:
- a memory region from which first data and second data are sequentially read;
- a storage circuit suitable for storing the first data and outputting the stored first data as third data when the second data is read;
- a control circuit suitable for generating a reset control signal and an input data control signal based on the first to third data;
- a power supply circuit suitable for generating a high voltage and a low voltage each having a target level during a first output enable period and a second output enable period, in response to the reset control signal, and transitioning each of the high and low voltages from the target level to a reset level or maintaining each of the high and low voltages at the target level, according to a logical relationship between the second data and the third data during an output disable period between the first output enable period and the second output enable period;
- and
- an output circuit suitable for receiving the high and low voltages, and outputting first output data corresponding to the first data to a data pad during the first output enable period and outputting second output data corresponding to the second data to the data pad during the second output enable period, based on the input data control signal,
- wherein the control circuit determines whether to activate the input data control signal according to the first data during the first output enable period,
- wherein the control circuit deactivates the input data control signal regardless of the second data during the second output enable period when a logic level of the second data is equal to a logic level of the third data, and determines whether to activate the input data control signal according to the second data during the second output enable period when the logic level of the second data is different from the logic level of the third data, and
- wherein the control circuit deactivates an input data control circuit during the output disable period.
6 more elements
A semiconductor memory device comprising:
- a memory region from which first data and second data are sequentially read;
- a storage circuit suitable for storing the first data and outputting the stored first data as third data when the second data is read;
- a control circuit suitable for generating a reset control signal and an input data control signal based on the first to third data;
- a power supply circuit suitable for generating a high voltage and a low voltage each having a constant voltage level;
- and
- an output circuit suitable for receiving the high and low voltages, and sequentially outputting first output data and second output data corresponding to the first data and the second data, respectively, to a data pad by controlling an internal current during a first output enable period and a second output enable period and performing or skipping a reset operation on the data pad by adjusting a resistance value of a path of the internal current during an output disable period between the first and second output enable periods, in response to the reset control signal and the input data control signal,
- wherein the control circuit determines whether to activate the input data control signal according to the first data during the first output enable period,
- wherein the control circuit deactivates the input data control signal regardless of the second data during the second output enable period when a logic level of the second data is equal to a logic level of the third data, and determines whether to activate the input data control signal according to the second data during the second output enable period when the logic level of the second data is different from the logic level of the third data, and
- wherein the control circuit deactivates an input data control circuit during the output disable period.
6 more elements
A transmitter comprising:
- an output circuit including a storage circuit, the output circuit configured to output first data during a first output enable period and output second data during a second output enable period, to a data output terminal in a superconducting state or a voltage state depending on values of the first and second data;
- a control circuit configured to generate a reset control signal and an input data control signal based on the first and second data;
- and
- a power supply circuit configured to supply a high voltage and a low voltage which have target levels during the first and second output enable periods, to the output circuit,
- wherein, when the first and second data have different values, the high voltage and the low voltage have reset levels during an output disable period between the first and second output enable periods, and
- when the first and second data have a same value, the high voltage and the low voltage maintain target levels during the output disable period,
- wherein the storage circuit is configured to store sequentially inputted data and sequentially output the stored data as the first and second data, and output the stored first data as third data when the second data is read,
- wherein the control circuit determines whether to activate the input data control signal according to the first data during the first output enable period,
- wherein the control circuit deactivates the input data control signal regardless of the second data during the second output enable period when a logic level of the second data is equal to a logic level of the third data, and determines whether to activate the input data control signal according to the second data during the second output enable period when the logic level of the second data is different from the logic level of the third data, and
- wherein the control circuit deactivates an input data control circuit during the output disable period.
7 more elements
A transmitter comprising:
- a transmission circuit configured to output first data during a first output enable period and output second data during a second output enable period, to an output terminal in a superconducting state or a voltage state depending on values of the first and second data;
- a storage circuit configured to store sequentially inputted data and sequentially output the stored data as the first and second data;
- a control circuit suitable for generating a reset control signal and an input data control signal based on the first data and the second data;
- and
- a variable resistance element coupled to at least one of first and second supply voltage terminals of the transmission circuit, and configured to have, in response to the reset control signal, a first resistance value to allow at least a supply voltage having constant target level to be supplied to the transmission circuit during the first and second data output enable periods, and a second resistance value to block supplying of the supply voltage to the transmission circuit during an output disable period between the first and second output enable periods,
- wherein, when the first and second data have a same value, the reset control signal is deactivated to allow at least the supply voltage to be supplied to the transmission circuit during the output disable period,
- wherein the storage circuit is suitable for storing the first data and outputting the stored first data as third data when the second data is read,
- wherein the control circuit determines whether to activate the input data control signal according to the first data during the first output enable period, wherein the control circuit deactivates the input data control signal regardless of the second data during the second output enable period when a logic level of the second data is equal to a logic level of the third data, and determines whether to activate the input data control signal according to the second data during the second output enable period when the logic level of the second data is different from the logic level of the third data, and
- wherein the control circuit deactivates an input data control circuit during the output disable period.
6 more elements
Dependencies are inferred from the claim text.