Quarter rate speculative decision feedback equalizer (DFE) and method for operating thereof

A method for operating a quarter rate speculative decision feedback equalizer (DFE) in a communication system, the method comprising:

• receiving, by the quarter rate speculative DFE, an input signal comprising a plurality of symbols;
• sampling, by the quarter rate speculative DFE, the input signal that was received into a plurality of streams of data samples in parallel, wherein the plurality of streams of data samples are sampled by different clock phases at a specified data rate;
• simultaneously performing, by the quarter rate speculative DFE, an align operation and a look ahead operation on the plurality of streams of data samples and the different clock phases to obtain a plurality of latched outputs;
• and
• generating, by the quarter rate speculative DFE, two speculative data streams by multiplexing respective correction coefficients of each of the plurality of latched outputs,
• wherein ones of the plurality of latched outputs are output from a first latch, a second latch, a third latch, and a fourth latch,
• wherein the quarter rate speculative DFE comprises a plurality of quarter rate look ahead circuits that comprise:
• a first flip flop connected to the first latch, wherein the first flip flop is configured to receive a first Non-Return to-Zero (NRZ) signal from the first latch and samples the first NRZ signal with a first clock phase in a first pipelining stage, and wherein a first output of the first flip flop is latched and triggered by a fifth latch using a second clock phase to generate a first latched output of the plurality of latched outputs;
• a second flip flop connected to the fifth latch;
• a third flip flop connected to the second latch, wherein the third flip flop is configured to receive a second NRZ signal from the second latch, wherein the second NRZ signal is sampled by a third clock phase in a second pipelining stage, wherein a second output of the third flip flop is latched using a fourth clock phase to generate a second latched output of the plurality of latched outputs, and wherein the third clock phase is different from the fourth clock phase;
• a fourth flip flop that operates responsive to a sixth latch;
• a fifth flip flop connected to a sixth flip flop, wherein the fifth flip flop is driven by the third clock phase, wherein the fifth flip flop is configured to receive a third NRZ signal from the third latch, and wherein the third NRZ signal is sampled by a fifth clock phase in a third pipelining stage to generate a third latched output of the plurality of latched outputs;
• and
• a seventh flip flop that is configured to trigger an eighth flip flop, wherein the seventh flip flop is driven by the fourth clock phase, wherein the seventh flip flop is configured to receive a fourth NRZ signal from the fourth latch, and wherein the fourth NRZ signal is sampled by a sixth clock phase in a fourth pipelining stage to generate a fourth latched output of the plurality of latched outputs.

A quarter rate speculative decision feedback equalizer (DFE), comprising:

• an input terminal configured to receive an input signal comprising a plurality of symbols;
• a plurality of sampler circuits configured to sample the input signal that was received and generate a plurality of data samples in parallel, wherein the plurality of sampler circuits use a plurality of different clock phases at a specified data rate;
• and
• a plurality of quarter rate look ahead circuits that are connected to the plurality of sampler circuits and are configured to simultaneously perform an align operation and a look ahead operation on the plurality of data samples based on the plurality of different clock phases to obtain a plurality of latched outputs,
• wherein the plurality of quarter rate look ahead circuits comprise a plurality of multiplexers that are configured to select a corresponding one of two respective speculative data streams generated by multiplexing respective correction coefficients of each of the plurality of latched outputs,
• wherein first and second select lines of corresponding ones of the plurality of multiplexers are driven based on one of data outputs of the plurality of quarter rate look ahead circuits, and
• wherein third and fourth select lines of corresponding ones of the plurality of multiplexers are driven based on a multiplexer output of one of the plurality of multiplexers,
• wherein ones of the plurality of latched outputs are from a first latch, a second latch, a third latch, and a fourth latch of the plurality of sampler circuits, and
• wherein the plurality of quarter rate look ahead circuits comprise:
• a first flip flop connected to the first latch, wherein the first flip flop is configured to receive a first Non-Return to-Zero (NRZ) signal from the first latch and to sample the first NRZ signal with a first clock phase in a first pipelining stage, and wherein a first output of the first flip flop is latched and triggered by a fifth latch using a second clock phase to generate a first latched output of the plurality of latched outputs;
• a second flip flop connected to the fifth latch;
• a third flip flop connected to the second latch, wherein the third flip flop is configured to receive a second NRZ signal from the second latch, wherein the second NRZ signal is sampled by a third clock phase in a second pipelining stage, wherein a second output of the third flip flop is latched using a fourth clock phase to generate a second latched output of the plurality of latched outputs, and wherein the third clock phase is different from the fourth clock phase;
• a fourth flip flop that is configured to operate responsive to a sixth latch;
• a fifth flip flop connected to a sixth flip flop, wherein the fifth flip flop is driven by the third clock phase, wherein the fifth flip flop is configured to receive a third NRZ signal from the third latch, wherein the third NRZ signal is sampled by a fifth clock phase in a third pipelining stage to generate a third latched output of the plurality of latched outputs;
• and
• a seventh flip flop that is configured to trigger an eighth flip flop, wherein the seventh flip flop is driven by the fourth clock phase, wherein the seventh flip flop is configured to receive a fourth NRZ signal from the fourth latch, and wherein the fourth NRZ signal is sampled by a sixth clock phase in a fourth pipelining stage to generate a fourth latched output of the plurality of latched outputs.