Low-power and area-efficient gain-bandwidth tripler amplifier
AssigneeIntel Corporation
InventorsSaurabh Anmadwar, Dheeraj Shetty, Madhuban Kishor
Life of this patent
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Abstract
An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.
Claims18
An apparatus, comprising:
- a first input and a second input;
- a first transconductance component and a second transconductance component;
- a first feedforward path where the first input is coupled to a gate of the first transconductance component;
- a second feedforward path where the second input is coupled to a gate of the second transconductance component;
- a first capacitor coupled to the second input and a source of the first transconductance component;
- a second capacitor coupled to the first input and a source of the second transconductance component;
- a first input transistor to receive the first input, wherein the first input transistor is coupled in series with the first transconductance component;
- a second input transistor to receive the second input, wherein the second input transistor is coupled in series with the second transconductance component;
- and
- a current source, wherein the first input transistor and the second input transistor are coupled to the current source.
An apparatus, comprising:
- first and second transistors in a first pair of transistors, wherein the first pair of transistors are coupled to a current source;
- third and fourth transistors in a second pair of transistors, wherein the first transistor is coupled in series with the third transistor, and the second transistor is coupled in series with the fourth transistor;
- a first input coupled to a gate of the first transistor;
- a second input coupled to a gate of the second transistor;
- a first path to couple the first input to a gate of the third transistor via a first capacitor;
- a second path to couple the second input to a gate of the fourth transistor via a second capacitor;
- a third input coupled to a source of the third transistor via a third capacitor;
- and
- a fourth input coupled to a source of the fourth transistor via a fourth capacitor;
- wherein the first and fourth inputs are coupled to a first voltage signal, and the second and third inputs are coupled to a second voltage signal.
An apparatus, comprising:
- a first input and a second input;
- a first transistor and a second transistor;
- a first capacitor having a first terminal coupled to the first input and a second terminal coupled to a gate of the first transistor;
- a second capacitor having a first terminal coupled to the second input and a second terminal coupled to a gate of the second transistor;
- a third capacitor coupled to the second input and a source of the first transistor;
- a fourth capacitor coupled to the first input and a source of the second transistor;
- a first resistive device coupled to the gate of the first transistor;
- and
- a second resistive device coupled to the gate of the second transistor, wherein the first resistive device is coupled in series with the second resistive device.
Dependencies are inferred from the claim text.