US 11,476,336 B2Granted

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorsHiroshi Ono, Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Aya Shindome, Masahiko Kuraguchi

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Abstract

According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, and a first compound member. A position of the third electrode is between a position of the second electrode and a position of the first electrode. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the third and first partial regions. The fifth partial region is between the second and third partial regions. The second semiconductor layer includes first, second, and third semiconductor regions. The third semiconductor region is between the first partial region and the first electrode. The first compound member includes first compound portions between the third semiconductor region and the first electrode. A portion of the first electrode is between one of the first compound portions and an other one of the first compound portions.

Claims18

Dependent claims

A semiconductor device, comprising:

a first electrode;
a second electrode;
a third electrode, a position of the third electrode in a first direction being between a position of the second electrode in the first direction and a position of the first electrode in the first direction, the first direction being from the second electrode toward the first electrode;
a first semiconductor layer including Alx1Ga1-x1N (0≤x1<1), the first semiconductor layer including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a second direction from the first partial region toward the first electrode crossing the first direction, a direction from the second partial region toward the second electrode being aligned with the second direction, a direction from the third partial region toward the third electrode being aligned with the second direction, the fourth partial region being between the third partial region and the first partial region in the first direction, the fifth partial region being between the second partial region and the third partial region in the first direction;
a second semiconductor layer including Alx2Ga1-x2N (0<x2<1 and x1<x2), the second semiconductor layer including a first semiconductor region, a second semiconductor region, and a third semiconductor region, a direction from the fourth partial region toward the first semiconductor region being aligned with the second direction, a direction from the fifth partial region toward the second semiconductor region being aligned with the second direction, the third semiconductor region being between the first partial region and the first electrode in the second direction, a portion of the third electrode being provided between the second semiconductor region and the third semiconductor region in the first direction;
a first compound member including Aly1Ga1-y1N (0<y1≤1 and x2<y1) and including a plurality of first compound portions, the plurality of first compound portions being between the third semiconductor region and the first electrode in the second direction, a portion of the first electrode being between one of the plurality of first compound portions and another one of the plurality of first compound portions in the first direction, the third electrode not overlapping the first compound member in the second direction;
and
a first insulating layer, a first portion of the first insulating layer being provided (1) between the third partial region and the portion of the third electrode in the second direction, and (2) between the fourth partial region and the fifth partial region in the first direction,
the first insulating layer continuously extending from the third electrode to the first electrode, and
the entire continuous extension of the first insulating layer from the third electrode to the first electrode directly contacting the second semiconductor layer.

7 more elements

A semiconductor device, comprising:

a first electrode;
a second electrode;
a third electrode, a position of the third electrode in a first direction being between a position of the second electrode in the first direction and a position of the first electrode in the first direction, the first direction being from the second electrode toward the first electrode;
a first semiconductor layer including Alx1Ga1-x1N (0≤x1<1), the first semiconductor layer including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a second direction from the first partial region toward the first electrode crossing the first direction, a direction from the second partial region toward the second electrode being aligned with the second direction, a direction from the third partial region toward the third electrode being aligned with the second direction, the fourth partial region being between the third partial region and the first partial region in the first direction, the fifth partial region being between the second partial region and the third partial region in the first direction;
a second semiconductor layer including Alx2Ga1-x2N (0<x2<1 and x1<x2), the second semiconductor layer including a first semiconductor region, a second semiconductor region, and a third semiconductor region, a direction from the fourth partial region toward the first semiconductor region being aligned with the second direction, a direction from the fifth partial region toward the second semiconductor region being aligned with the second direction, the third semiconductor region being between the first partial region and the first electrode in the second direction, a portion of the third electrode being provided between the second semiconductor region and the third semiconductor region in the first direction;
a first compound member including Aly1Ga1-y1N (0<y1≤1 and x2<y1) and including a plurality of first compound portions, the plurality of first compound portions being between the third semiconductor region and the first electrode in the second direction, a portion of the first electrode being between one of the plurality of first compound portions and another one of the plurality of first compound portions in the first direction, the third electrode not overlapping the first compound member in the second direction;
and
a first insulating layer, a portion of the first insulating layer being provided (1) between the third partial region and the portion of the third electrode in the second direction, and (2) between the fourth partial region and the fifth partial region in the first direction,
the first insulating layer being continuous between the third electrode and the first electrode in the first direction, and
the first compound member being not provided between the first semiconductor region and the first insulating layer in the second direction.

7 more elements

A semiconductor device, comprising:

a first electrode;
a second electrode;
a third electrode, a position of the third electrode in a first direction being between a position of the second electrode in the first direction and a position of the first electrode in the first direction, the first direction being from the second electrode toward the first electrode;
a first semiconductor layer including Alx1Ga1-x1N (0≤x1<1), the first semiconductor layer including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a second direction from the first partial region toward the first electrode crossing the first direction, a direction from the second partial region toward the second electrode being aligned with the second direction, a direction from the third partial region toward the third electrode being aligned with the second direction, the fourth partial region being between the third partial region and the first partial region in the first direction, the fifth partial region being between the second partial region and the third partial region in the first direction;
a second semiconductor layer including Alx2Ga1-x2N (0<x2<1 and x1<x2), the second semiconductor layer including a first semiconductor region, a second semiconductor region, and a third semiconductor region, a direction from the fourth partial region toward the first semiconductor region being aligned with the second direction, a direction from the fifth partial region toward the second semiconductor region being aligned with the second direction, the third semiconductor region being between the first partial region and the first electrode in the second direction, a portion of the third electrode being provided between the second semiconductor region and the third semiconductor region in the first direction;
a first compound member including Aly1Ga1-y1N (0<y1≤1 and x2<y1) and including a plurality of first compound portions, the plurality of first compound portions being between the third semiconductor region and the first electrode in the second direction, a portion of the first electrode being between one of the plurality of first compound portions and another one of the plurality of first compound portions in the first direction, the third electrode not overlapping the first compound member in the second direction;
a first insulating layer, a first portion of the first insulating layer being provided between the third partial region and the portion of the third electrode in the second direction, a second portion of the first insulating layer being provided between the second semiconductor region and the portion of the third electrode in the first direction, and a third portion of the first insulating layer being provided between the portion of the third electrode and the first semiconductor region in the first direction;
and
a fifth compound member including the Aly1Ga1-y1N, the fifth compound member being continuously provided at least (1) between the third partial region and the first portion of the first insulating layer in the second direction, (2) between the second semiconductor region and the second portion of the first insulating layer in the first direction, and (3) between the third portion of the first insulating layer and the first semiconductor region in the first direction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/787,351Filed 11 Feb 2020
Priority: JP JP2019-08007219 Apr 2019
Published: US 2020/0335587 A122 Oct 2020
Granted: 18 Oct 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 62/117
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes of semiconductor bodies
H10D 62/824
Heterojunctions: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 30/4732
Having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT: using Group III-V semiconductor material
H10D 30/475
High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]: having wider bandgap layer formed on top of lower bandgap…