IC including standard cells and SRAM cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). The P-type FinFETs includes at least one first P-type FinFET and at least one second P-type FinFET. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth. A first semiconductor fin of the first P-type FinFET includes a first portion and a second portion that are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.
Claims20
An integrated circuit (IC), comprising:
- a plurality of P-type fin field-effect transistors (FinFETs), comprising:
- at least one first P-type FinFET over a semiconductor substrate;
- and
- at least one second P-type FinFET over the semiconductor substrate,
- wherein source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth,
- wherein a first semiconductor fin of the first P-type FinFET comprises a first portion over the semiconductor substrate and a second portion over the first portion, wherein the first and second portions are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.
An integrated circuit (IC), comprising:
- a logic array comprising a plurality of logic cells arranged in rows and columns, wherein each of the logic cells comprises at least one first P-type fin field-effect transistor (FinFET);
- and
- a memory array comprising a plurality of memory cells arranged in rows and columns, wherein each of the memory cells comprises at least one second P-type FinFET,
- wherein a first semiconductor fin of the first P-type FinFET comprises a first portion and a second portion over the first portion, and the second portion of the first semiconductor fin and a second semiconductor fin of the second P-type FinFET comprise different materials,
- wherein the second portion of the first semiconductor fin, source/drain regions of the second P-type FinFET and source/drain regions of the first P-type FinFET have different depths.
An integrated circuit (IC), comprising:
- a plurality of first cells, wherein each of the first cells comprises a plurality of first P-type fin field-effect transistors (FinFETs);
- and
- a plurality of second cells, wherein each of the second cells comprises a plurality of second P-type FinFETs,
- wherein the first P-type FinFETs of each of the first cells share a discontinuous semiconductor fin comprising a first portion and a second portion over the first portion, and the second P-type FinFETs of the second cells positioned in a first line share a continuous semiconductor fin,
- wherein the first and second portions are formed by different materials, and
- wherein the second portion of the discontinuous semiconductor fin, source/drain regions of the second P-type FinFETs and source/drain regions of the first P-type FinFETs have different depths.
Dependencies are inferred from the claim text.