US 11,476,242 B2Granted

Cascode power electronic device packaging method and packaging structure thereof

AssigneeUltraband Technologies, Inc.

InventorsTai-Hui Liu, Chung-Hsi Liu

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Abstract

The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.

Claims10

Dependent claims

A packaging method for a cascode power electronic device, comprising:

providing a substrate and disposing a pressure sensitive adhesive layer on the substrate;
disposing more than one gallium nitride semiconductor die, more than one diode and more than one metal oxide semiconductor transistor on the pressure sensitive adhesive layer;
coating a first photo-developing layer on the pressure sensitive adhesive layer, the first photo-developing layer covering the gallium nitride semiconductor die, the diode and the metal oxide semiconductor transistor;
exposing and developing a first surface of the first photo-developing layer on the gallium nitride semiconductor die, the diode, and metal oxide semiconductor transistor, and plating copper on the exposed and developed area to form a copper plating layer;
disposing a first plastic layer on the first photo-developing layer, the first plastic layer covering the unexposed development area on the first photo-developing layer and the copper plating layer, and providing a heat sink on the first plastic layer;
peeling the substrate and the pressure sensitive adhesive layer;
coating a second photo-developing layer on a second surface of the first photo-developing layer, and the second photo-developing layer covering the gallium nitride semiconductor die, the diode, and metal oxide semiconductor transistor;
exposing and developing the second photo-developing layer to reveal a gate and a drain of the gallium nitride semiconductor die, a drain and a source of the metal oxide semiconductor transistor and the diode;
forming a redistribution layer on the gate and the drain of the gallium nitride semiconductor die, the drain and the source of the metal oxide semiconductor transistor and the diode;
plating a protective layer on the redistribution layer;
and
adhering a blue tape on a ceramic heat sink, and dicing the gallium nitride semiconductor die, the diode, the metal oxide semiconductor transistor, the first plastic layer and the ceramic heat sink to form a plurality of package modules;
connecting the package modules to each other only through the blue tape;
stretching the blue tape to increase gaps between the package modules;
removing the blue tape to obtain the plurality of package modules;
and cascading with the plurality of package modules to form a power electronic device.

13 more elements

A packaging method for a cascode power electronic device, comprising:

providing a substrate and disposing a pressure sensitive adhesive layer on the substrate;
disposing more than one gallium nitride semiconductor die, more than one diode, more than one metal oxide semiconductor transistor and more than one metal block on the pressure sensitive adhesive layer;
coating a first photo-developing layer on the pressure sensitive adhesive layer, the first photo-developing layer covering the gallium nitride semiconductor die, the diode, the metal oxide semiconductor transistor and the metal block;
exposing and developing a first surface of the first photo-developing layer on the gallium nitride semiconductor die, the metal oxide semiconductor transistor, the diode and the metal block, and plating copper on the exposed and developed area to form a copper plating layer;
disposing a first plastic layer on the first photo-developing layer, the first plastic layer covering on the unexposed development area and the copper plating layer, and providing a heat sink on the first plastic layer;
peeling the substrate and the pressure sensitive adhesive layer;
coating a second photo-developing layer on a second surface of the first photo-developing layer, and the second photo-developing layer covering the gallium nitride semiconductor die, the diode, the metal oxide semiconductor transistor and the metal block;
exposing and developing the second photo-developing layer to reveal a drain of the gallium nitride semiconductor die, a gate and a source of the metal oxide semiconductor transistor, the diode and the metal block;
plating metal on the exposed area to form a metal layer;
plating a protective layer on the metal layer;
and
adhering a blue tape on a ceramic heat sink, and dicing the gallium nitride semiconductor die, the diode, the metal oxide semiconductor transistor, the metal block, the first plastic layer and the ceramic heat sink to form a plurality of package modules;
connecting the package modules to each other only through the blue tape;
stretching the blue tape to increase gaps among the package modules;
removing the blue tape to obtain the plurality of package modules;
and cascading with the plurality of package modules to form a power electronic device.

13 more elements

Dependencies are inferred from the claim text.