Memory cell arrangement and methods thereof

Memory cell arrangement comprising:

• a memory cell comprising a spontaneous-polarizable memory layer, and
• a control circuit configured to cause a writing of the memory cell by a single writing operation, wherein the single writing operation comprises:
• carrying out a writing sequence, the writing sequence comprising:
• supplying a write signal set to the memory cell to provide a write voltage drop to bring the memory cell in a memory state by polarizing the spontaneous-polarizable memory layer, and, subsequently,
• supplying a post-conditioning signal set to the memory cell to provide a post-conditioning voltage drop having opposite polarity with respect to the write voltage drop to partially depolarize the spontaneous-polarizable memory layer;
• and
• checking, after carrying out the writing sequence, whether the memory cell still resides in the memory state, and either repeating the writing sequence and the checking in the case that the memory cell does not reside in the memory state, or ending the single writing operation by repeating only the writing sequence in the case that the memory cell resides in the memory state.

A method of writing a memory cell, the method comprising:

• bringing a memory cell into a memory state of at least two memory states by applying a write signal set to the memory cell;
• verifying a robustness of the memory state by applying a disturb signal set to the memory cell after the memory cell is brought into the memory state;
• and
• either ending the writing of the memory cell in the case that the robustness of the memory state is verified or applying a further write signal set to the memory cell to bring the memory cell into a more robust memory state.