Circuit for improving edge-rates in voltage-mode transmitters

A method for controlling a driver circuit comprising:

• receiving, at a control circuit, an input data signal and a clock signal;
• generating a control signal based on the data signal and the clock signal comprising:
• delaying the input data signal by at least one clock cycle, and
• generating the control signal having a first logic level in response to the input data signal and the delayed input data signal having a same logic level, and a second logic level in response to the input data signal and the delayed input data signal having different logic levels;
• and
• controlling a third pull-up transistor of a pull-up network based on the control signal, the third pull-up transistor in parallel with a second pull-up transistor, the third pull-up transistor coupled between a first pull-up transistor and a first power supply voltage, comprising:
• turning on the third pull-up transistor responsive to the input data signal and the delayed input data signal having different logic levels.

A non-transitory computer readable storage medium storing a design of a driver circuit, the design of the driver circuit comprising:

• a control circuit having a first input terminal for receiving an input data signal, a second input terminal for receiving a clock signal wherein the control circuit is configured to delay the input data signal by at least one clock cycle, and generate the control signal having a first logic level in response to the input data signal and the delayed input data signal having a same logic level, and a second logic level in response to the input data signal and the delayed input data signal having different logic levels;
• and
• a pull-up network having:
• a first pull-up transistor controlled by a input data signal;
• a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage;
• and
• a third pull-up transistor, the third pull-up transistor coupled in parallel with the second pull-up transistor, a gate terminal of the third pull-up transistor coupled to an output terminal of the control circuit providing the control signal, the control signal configured to turn on the third pull-up transistor responsive to the input data signal and the delayed input data signal having different logic levels.