Circuits and methods for maintaining gain for a continuous-time linear equalizer

A method for operating an equalizer circuit, the method comprising:

• at a first bias circuit having a first transistor and a second transistor arranged in separate legs of a current mirror, maintaining a drain voltage of the first transistor and a drain voltage of the second transistor equal to a gate voltage of the first transistor;
• generating a current by a first current source in series with legs of the current mirror, wherein a gate voltage of the first current source is provided by a first operational amplifier (op amp) disposed between a gate of the first transistor and a drain of the second transistor;
• applying the gate voltage to a second current source within the equalizer circuit;
• maintaining a transconductance times resistance (gm*R) of the first bias circuit constant over a range of process corners, operating voltages and operating temperatures;
• and
• maintaining a gm*R of the equalizer circuit to be equal to the gm*R of the first bias circuit.

A semiconductor chip comprising:

• a first bias circuit having a first transistor and a second transistor arranged in a first current mirror, the first bias circuit further having a first current source coupled to the first transistor and the second transistor, the first bias circuit further having a first operational amplifier (op amp) coupled to a drain of the second transistor and a gate of the first transistor and coupled to output a first bias voltage to a gate of the first current source;
• a second bias circuit having a second op amp coupled to output a second bias voltage to a gate of a third transistor;
• and
• an equalizer circuit having a fourth transistor and a fifth transistor are arranged in a second current mirror, the fourth transistor being in series with a second current source, the second current mirror coupled to a power rail by a sixth transistor, wherein the second current source is coupled to the first bias voltage, and wherein the sixth transistor is coupled to the second bias voltage.

A data receiver in a semiconductor chip, the data receiver comprising:

• means for reshaping a differential data signal, including applying a gain to the differential data signal, wherein the gain equals a transconductance of a first transistor times a resistance;
• means for adjusting a current through the first transistor, including means for applying a bias voltage to a current source in the reshaping means, wherein the bias voltage applying means includes:
• a second transistor and a third transistor arranged in a current mirror architecture;
• and
• a first operational amplifier (op amp) coupled to a drain of the second transistor and to a gate of the third transistor and having a feedback loop configured to adjust the bias voltage;
• and
• means for deserializing the differential data signal.