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US 11,467,973 B1Granted
Fine-grained access memory controller
AssigneeAmazon Technologies, Inc.
InventorsRon Diamant, Sundeep Amirineni
Life of this patent
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Abstract
Systems and methods are provided to perform fine-grained memory accesses using a memory controller. The memory controller can access elements stored in memory across multiple dimensions of a matrix. The memory controller can perform accesses to non-contiguous memory locations by skipping zero or more elements across any dimension of the matrix.
Claims16
A pooling engine for a neural network processor, the pooling engine having a memory controller configured to:
- receive a set of parameters from a computation controller of the neural network processor, the computation controller being physically separate from the pooling engine, the set of parameters having been decoded by the computation controller from instructions to perform a pooling operation, wherein the set of parameters includes:
- a start address to access elements stored in memory;
- a first count indicator corresponding to a number of elements to be accessed in a first dimension;
- a second count indicator corresponding to a number of elements to be accessed in a second dimension;
- a first address offset corresponding to an address increment between each of the elements to be accessed in the first dimension;
- and
- a second address offset corresponding to an address increment between each of the elements to be accessed in the second dimension;
- and
- access the elements by accessing a respective address for each of the elements to be accessed based on the start address, the first count indicator, the second count indicator, the first address offset, and the second address offset such that one or more elements in the memory are skipped when accessing the elements in the memory, wherein the memory controller is configured to access the elements via a memory interface and bring the elements into the pooling engine for performing pooling operations on the elements.
6 more elements
A method comprising:
- receiving, by a memory controller of a pooling engine for a neural network processor, a set of parameters from a computation controller of the neural network processor, the computation controller being physically separate from the pooling engine, the set of parameters having been decoded by the computation controller from instructions to perform a pooling operation, wherein the set of parameters includes:
- a start address to access elements stored in memory;
- a first count indicator corresponding to a number of elements to be accessed in a first dimension;
- a second count indicator corresponding to a number of elements to be accessed in a second dimension;
- a first address offset corresponding to an address increment between each of the elements to be accessed in the first dimension;
- and
- a second address offset corresponding to an address increment between each of the elements to be accessed in the second dimension;
- and
- accessing, by the memory controller, the elements by accessing a respective address for each of the elements to be accessed based on the start address, the first count indicator, the second count indicator, the first address offset, and the second address offset such that one or more elements in the memory are skipped when accessing the elements in the memory, wherein the memory controller is configured to access the elements via a memory interface and bring the elements into the pooling engine for performing pooling operations on the elements.
6 more elements
Dependencies are inferred from the claim text.