Method of testing one or more compute units

A processor, comprising:

• a plurality of compute units each comprising a multiplier and an adder;
• one or more test pattern generators configured to generate one or more test patterns and input the one or more test patterns into each of the multiplier and adder within a compute unit of the one or more of the plurality of compute units, wherein the one or more test pattern generators is configured to generate one or more test patterns during testing to cause the compute unit to generate a test pattern solution, which testing includes processing of the one or more test patterns by at least one of the multiplier and adder within the compute unit of the one or more of the plurality of compute units to test the multiplier element and the adder element of the compute unit separately;
• one or more control and sequencing logic units, configured to identify at least one idle period during use of the processor in which the compute unit of the plurality of compute units is deemed to be idle, to control a test pattern generator to generate and input test data to at least one of the multiplier and adder within the compute unit, the test data including at least a portion of the one or more test patterns, and control at least one of the multiplier and adder within the compute unit to process the test data during the idle period;
• and
• one or more comparators configured to compare the test pattern solution, with an expected test pattern solution.