Digital approximate multipliers for machine learning and artificial intelligence applications

An approximate digital multiplication method in a digital state machine in an integrated circuit, the method comprising:

• operating a digital cell (Z), the digital cell (Z) comprising:
• a pair of digital input ports (Px,Py) for receiving a pair of digital input words (x,y), a pair of digital output ports (PXo,PYo) for outputting a pair of digital output words (Xo,Yo), wherein the pair of digital input words (x,y) span between a negative full-scale (−FS) and a positive full-scale (+FS);
• computing each digital output word Xo of the digital cell (Z) as a function of an f-scaled absolute value of a sum of the digital input word x plus the digital input wordy minus the f-scaled absolute value of the digital input word x minus the digital input word y;
• computing each digital output word Yo of the digital cell (Z) as a function of the f-scaled absolute value of a sum of the digital input word x plus the digital input word y plus the f-scaled absolute value of the digital input word x minus the digital input word y minus the positive full-scale (+FS);
• wherein
• 1
• 2
• m
• <
• f
• <
• 2
• m
• wherein 0<m<10;
• operating a plurality (n) of the digital cell (Z);
• programming an interpolating approximate digital multiplier with a plurality of n digital interpolation stages from a first digital interpolation stage i=0 up to a last digital interpolation stage i=n−1, wherein n is a total number of digital interpolation stages, and wherein each interpolation stage comprises at least one of the digital cell (Z);
• cascading a sequence of n of the digital cell (Z)s beginning with a first digital cell (Z) in the sequence corresponding to i=0 and ending with a last digital cell (Z) in the sequence corresponding to i=n−1;
• the pair of digital output ports (PXo,PYo) of the first digital cell (Z) communicating with the respective pair of digital input ports (Px,Py) of a second digital cell (Z) in the sequence corresponding to i=1;
• the pair of digital output ports (PXo,PYo) of each successive digital cell (Z) in the sequence communicating with the respective pair of digital input ports (Px,Py) of each subsequent successive digital cell (Z) in the cascaded sequence of the plurality (n) of the digital cell (Z)s;
• and
• wherein 1≤n≤10 and 1≤i+1≤10.