# US 11,467,653 B2 · Systems and methods for power management in low power communication device and system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,467,653 B2 - Document ID: US11467653B2 - Status: Granted - Kind: B2 - Application number: 17/003,899 - Filed: 2020-08-26 - Published: 2020-12-17 - Granted: 2022-10-11 - Earliest claimed: 2017-02-27 - Assignees: Ubilite, Inc. - Applicants: ubilite, Inc. - Inventors: Ismail Lakkis; Lai Xu - Web page: https://patentgrep.com/patent/US11467653B2 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)} - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/3237: by disabling clock generation or distribution - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A radio module, comprises a battery; and a radio circuit, the radio circuit comprising: a DC-to-DC converter coupled with the batters and configured to convert a battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to covert the first DC voltage level to a second DC voltage level; at least one circuit block coupled with the at least one regulator such that the second DC voltage level is configured to provide power to the at least one circuit block; a real time clock configured to provide a clock signal to the at least one circuit block; and a management unit coupled with the at least one circuit block and configured to implement a state machine to control the at least one circuit block, wherein the state machine causes the management unit to cause the second DC voltage level to be removed from the at least one circuit during a first state comprising the state machine and, during a second state comprising the state machine, cause the second DC voltage level to be provided to the at least one circuit block, cause certain components within the circuit block to be reset, and provide a start signal to the circuit block enabling the circuit block to perform a function, and wherein the circuit block is configured to generate a signal indicating the function has been completed that is provided to the management unit, which causes the state machine to transition to a third state in which the second DC voltage is gain removed from the at least one circuit block. ## Claims ### Claim 1 A method within a hardware programmable state machine comprising, a plurality of circuit blocks, and a management unit communicatively coupled with the plurality of circuit blocks and configured to implement a hardware programmable state machine defined by a dynamically created, application specific power profile having a plurality of application specific power events, each power event comprising a plurality of transitions between a plurality of power states, each power state defining a different operational state for the plurality of circuit blocks, the method comprising: based on a specific application, automatically selecting from a plurality of power events only those power events needed to perform the functions required for the specific application, so as to ensure the lowest possible power consumption and longest possible battery life, the selected power events of the plurality of power events constituting the application specific power events and defining the application specific power profile; generating programming instructions configured to cause the management unit circuit to implement the application specific power profile; and transmitting programming instructions to the hardware programmable state machine, wherein the plurality of power states comprises at least some of a power off state (S0), and awake state (S1), and initialized state (S2), an active state (S3), an active transmitting state (S3tx), an active receiving state (S3rx), a sleep state (S4), a listen state (S5), a deep sleep state (S6), and a hibernate state (S7), and wherein the plurality of application specific power events comprise a combination of a cold boot event (E1), a warm boot event (E2), an active event (E3), a listen event (E4), a second listen event (E5), a hibernate event (E6), and a power save event (E7); wherein, based on the programming instructions, the management circuit causes a DC-to-DC converter to shift from supplying a first voltage to supplying a second voltage to at least one of the plurality of circuit blocks. ### Claim 2 (depends on 1) The method of claim 1, wherein the power events comprise the following power states and transitions: E1 comprises an S0 to S1 transition, followed by an S1 to S2 transition, followed by an S2 to S3 transition; E2 comprises an S7 to S2 transition, followed by an S2 to S3 transition; E3 comprises an S0 to S1 transition, followed by an S1 to S2 transition, followed by an S2 to S3 transition; E4 comprises an S3 to S5 transition, followed by an S5 to S3tx transition; E5 comprises an S3 to S5 transition, followed by an S5 to S3rx transition; E6 comprises an S3 to S7 transition, followed by an S7 to S2 transition, followed by an S2 to S3 transition; and E7 comprises an S3 to S4 transition, followed by an S4 to S3 transition. ### Claim 3 (depends on 1) The method of claim 1, wherein the application specific power profile is one of an active profile (P0), an active deep sleep profile (P1), a listen profile (P2), a deep sleep profile (P3), and a hibernate profile (P4). ### Claim 4 (depends on 3) The method of claim 3, wherein the power profiles comprise the following power events and transitions: P0 comprises an E1 to E3 transition, followed by an E3 to E7 transition, followed by a repeating cycle through E7; P1 comprises an E1 to E3 transition, followed by an E3 to E4 transition, followed by a repeating cycle through E4; P2 comprises an E1 to E3 transition, followed by an E3 to E5 transition, followed by a repeating cycle through E5; P3 comprises an E1 to E4, followed by a repeating cycle through E4; and P4 comprises an E1 to E3 transition, followed by an E3 to E6 transition, followed by a repeating cycle through E6. ### Claim 5 A hardware programmable state machine comprising: a DC-to-DC converter coupled with a battery and configured to convert the battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to convert the first DC voltage level to a second DC voltage level; a plurality of circuit blocks, and a management unit communicatively coupled with the plurality of circuit blocks and configured to implement the hardware programmable state machine defined by a dynamically created, application specific power profile having a plurality of application specific power events, each power event comprising a plurality of transitions between a plurality of power states, each power state defining a different operational state for the plurality of circuit blocks, the hardware programmable state machine configured to: receive programming instructions configured to cause the management unit circuit to implement the application specific power profile; and implement the power profile as instructed by implementing the corresponding plurality of application specific power events, wherein the corresponding plurality of application specific power events causes the management unit to: cause the second DC voltage level to be provided to at least one of the plurality of circuit blocks during an operational state defined by the corresponding plurality of application specific power events, cause at least a portion of the at least one circuit block of the plurality of circuit blocks to be reset, provide a start signal to the at least one circuit block enabling the at least one circuit block to perform a function, receive from the at least one circuit block, prior to the transition from a current power state of the power states to a next power state of the power states, a signal indicating the function has been completed, and cause the second DC voltage to be removed from the at least one circuit block during the current power state. ### Claim 6 (depends on 5) The hardware programmable state machine of claim 5, wherein prior to the transition from the current power state to the next power state the management unit circuit is further configured to remove the clock signal from the at least one circuit block. ### Claim 7 (depends on 5) The hardware programmable state machine of claim 5, further comprising a switch coupled between the at least one regulator and the at least one circuit block, and wherein the management unit circuit is further configured to remove the second DC voltage from the at least one circuit block by controlling the switch. ### Claim 8 (depends on 5) The hardware programmable state machine of claim 5, further comprising a plurality of circuit blocks coupled with the at least one regulator, wherein the at least one regulator is configured to provide the second DC voltage to the plurality of circuit blocks, and wherein the management unit circuit is further configured to control each circuit block of the plurality of circuit blocks in the same manner as the at least one circuit block. ### Claim 9 (depends on 8) The hardware programmable state machine of claim 8, wherein the at least one regulator is a low drop out regulator. ### Claim 10 (depends on 8) The hardware programmable state machine of claim 8, wherein the plurality of circuit blocks comprises a microprocessor, a memory, a synthesizer, baseband transmit and receive blocks, and RF transmit and receive blocks. ### Claim 11 (depends on 8) The hardware programmable state machine of claim 8, wherein the plurality of circuit blocks comprises a retention memory configured to store register values and component values associated with the plurality of circuit blocks. ### Claim 12 (depends on 5) The hardware programmable state machine of claim 5, wherein the plurality of power states comprises at least some of a power off state (S0), and awake state (S1), and initialized state (S2), an active state (S3), an active transmitting state (S3tx), an active receiving state (S3rx), a sleep state (S4), a listen state (S5), a deep sleep state (S6), and a hibernate state (S7). ### Claim 13 (depends on 12) The hardware programmable state machine of claim 12, wherein during the deep sleep state, the second DC voltage is removed from all of the plurality of circuit blocks except the retention memory. ### Claim 14 (depends on 12) The hardware programmable state machine of claim 12, wherein the plurality of application specific power events comprise a combination of a cold boot event (E1), a warm boot event (E2), an active event (E3), a listen event (E4), a second listen event (E5), a hibernate event (E6), and a power save event (E7). ### Claim 15 (depends on 14) The hardware programmable state machine of claim 14, wherein the power events comprise the following power states and transitions: E1 comprises an S0 to S1 transition, followed by an S1 to S2 transition, followed by an S2 to S3 transition; E2 comprises an S7 to S2 transition, followed by an S2 to S3 transition; E3 comprises an S0 to S1 transition, followed by an S1 to S2 transition, followed by an S2 to S3 transition; E4 comprises an S3 to S5 transition, followed by an S5 to S3tx transition; E5 comprises an S3 to S5 transition, followed by an S5 to S3rx transition; E6 comprises an S3 to S7 transition, followed by an S7 to S2 transition, followed by an S2 to S3 transition; and E7 comprises an S3 to S4 transition, followed by an S4 to S3 transition. ### Claim 16 (depends on 14) The hardware programmable state machine of claim 14, wherein the application specific power profile is one of an active profile (P0), an active deep sleep profile (P1), a listen profile (P2), a deep sleep profile (P3), and a hibernate profile (P4). ### Claim 17 (depends on 16) The hardware programmable state machine of claim 16, wherein the power profiles comprise the following power events and transitions: P0 comprises an E1 to E3 transition, followed by an E3 to E7 transition, followed by a repeating cycle through E7, P1 comprises an E1 to E3 transition, followed by an E3 to E4 transition, followed by a repeating cycle through E4, P2 comprises an E1 to E3 transition, followed by an E3 to E5 transition, followed by a repeating cycle through E5, P3 comprises an E1 to E4, followed by a repeating cycle through E4, and P4 comprises an E1 to E3 transition, followed by an E3 to E6 transition, followed by a repeating cycle through E6.