Digital filter for second tap of DFE
AssigneeCadence Design Systems, Inc.
InventorMathieu Gagnon
Life of this patent
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Abstract
Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.
Claims20
A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors of a computing device, cause the computing device to generate a circuit design by performing operations comprising:
- configuring, in a circuit design, a first portion of a decision feedback equalizer configured to apply a first correction, including a first tap having a polarity and a second tap, to a first symbol of a data signal received by a data sampler circuit;
- configuring, in the circuit design, a second portion of the decision feedback equalizer configured to apply a second correction, including the first tap having an inverse polarity of the first tap of the first correction and the second tap, to the first symbol of the data signal, the first correction and the second correction being applied in parallel to the first symbol;
- configuring, in the circuit design, a multiplexer configured to receive an output of the first portion of the decision feedback equalizer, an output of the second portion of the decision feedback equalizer, and configured to select an output of either the first or second portion based upon a previous symbol of the data signal;
- and
- configuring, in the circuit design, a clock and data recovery circuit configured to receive an output of the multiplexer and an input of a previous data decision by the decision feedback equalizer.
A circuit, comprising:
- a data sampler circuit including a first portion for applying a first correction and a second portion for applying a second correction, a multiplexer coupled to the first and the second portions;
- and
- a clock data recovery circuit coupled to the data sampler circuit, wherein:
- the first portion of the data sampler circuit is configured to:
- receive a data signal including data symbols;
- apply a first correction on a first data symbol of the data signal, the first correction including a first tap having a polarity and a second tap;
- generate a first corrected data symbol based on the first correction;
- and
- output the first corrected data symbol;
- the second portion of the data sampler circuit is configured to:
- receive the data signal;
- apply a second correction on the first data symbol, the second correction including the first tap having an inverse polarity of the first tap of the first correction and the second tap;
- generate a second corrected data symbol based on the second correction;
- and
- output the second corrected data symbol;
- the multiplexer configured to:
- receive the first corrected data symbol;
- receive the second corrected data symbol;
- select the first or the second corrected data symbol;
- and
- output the selected corrected data symbol to the clock data recovery circuit.
A method, comprising:
- receiving a first data symbol of a data signal at a first portion of a data sampler circuit for applying a first correction;
- receiving the first data symbol at a second portion of the data sampler circuit for applying a second correction;
- applying a first correction to the first data symbol of the data signal including a first tap having a polarity and a second tap to generate a first corrected data symbol;
- applying a second correction to the first data symbol of the data signal including the first tap having an inverse polarity of the first tap of the first correction and the second tap, to generate a second corrected data symbol;
- providing the first and second corrected data symbols to a comparator;
- receiving a previous digital decision corresponding to a preceding data symbol of the data signal;
- providing an output of the comparator and the previous digital decision to a clock data recovery circuit;
- and
- selecting or rejecting the output of the comparator based upon the previous digital decision.
Dependencies are inferred from the claim text.