Multiple-digit binary in-memory multiplier devices

An operating method of an in-memory multiplication device that performs multiplication on a multiplicand and a multiplier to generate a final product, the in-memory multiplication device comprising a single in-memory multiplier unit, a first register unit, a second register unit, a number m of binary adder devices and zero or a number (m−1) of polynomial adders, the method comprising the steps of:

• comparing a first n-bit digit and a second n-bit digit respectively selected from the multiplicand and the multiplier with a number 22n of 2n-bit operand symbols hardwired in a first read-only-memory (ROM) array to output one of a number 22n of 2n-bit response symbols hardwired in a second ROM array as a 2n-bit product code and store the 2n-bit product code in the first register unit by the single in-memory multiplier unit comprising the first ROM array and the second ROM array;
• repeating the step of comparing until all digits of the multiplicand and the multiplier are processed and a number m2 of 2n-bit product codes are stored in the first register unit, wherein the number m2 of 2n-bit product codes serve as first coefficients of m first polynomials in base 2n, wherein the first coefficients of each first polynomial in base 2n are associated with multiplication of the multiplicand with a corresponding digit of the multiplier;
• when m>=2, sequentially adding a most significant digit of the first coefficient of a less degree term and a least significant digit of the first coefficient of a larger degree term adjacent to the less degree term for each first polynomial from the first register unit in ascending degree by each binary adder device comprising (m−1) n-bit adders and n half adders in a carry-chained configuration so that the 2n-bit first coefficients of the m first polynomials in base 2n are converted into n-bit second coefficients of m second polynomials in base 2n in parallel, wherein the number m of binary adder devices are arranged in a parallel configuration;
• and
• when m>=2, sequentially adding the m second polynomials in base 2n in ascending degrees by the number (m−1) of polynomial adders arranged in sequential order such that like terms of the m second polynomials in base 2n are lined up and added to generate and store a final product having 2m digits in base 2n in the second register unit, wherein each polynomial adder comprises a (m×n)-bit adder and n half adders in a carry-chained configuration;
• wherein each of the multiplicand and the multiplier has m digits in base 2n and both n and m are integers greater than 0.

An operating method of an in-memory multiplication device that performs multiplication on a multiplicand and a multiplier to generate a final product, the in-memory multiplication device comprising a number m of in-memory multiplier units in a parallel configuration, a first register unit, a second register unit, a binary adder device and zero or a number (m−1) of polynomial adders, the method comprising the steps of:

• comparing a first n-bit digit and a second n-bit digit respectively selected from the multiplicand and the multiplier with a number 22n of 2n-bit operand symbols hardwired in a first read-only-memory (ROM) array to output one of a number 22n of 2n-bit response symbols hardwired in a second read-only-memory (ROM) array as a 2n-bit product code by each in-memory multiplier unit comprising the first ROM array and the second ROM array so that a number m of 2n-bit product codes are outputted in parallel from the number m of in-memory multiplier units, wherein the number m of 2n-bit product codes serve as 2n-bit first coefficients of one of m first polynomials in base 2n and are associated with multiplication of the multiplicand with the second n-bit digit of the multiplier;
• when m>=2, sequentially adding a least significant digit of the first coefficient of a less degree term and a most significant digit of the first coefficient of a larger degree term adjacent to the less degree term in the one first polynomial in ascending degree by the binary adder device comprising (m−1) n-bit adders and n half adders in a carry-chained configuration to convert the 2n-bit first coefficients of the one first polynomial in base 2n into n-bit second coefficients of a corresponding second polynomial in base 2n and store the n-bit second coefficients of the corresponding second polynomial in base 2n in the first register unit;
• repeating steps of comparing and converting until all the digits of the multiplier are selected and all the n-bit second coefficients of m second polynomials in base 2n are stored in the first register unit;
• and
• when m>=2, sequentially adding the m second polynomials in base 2n in ascending degrees by the number (m−1) of polynomial adders arranged in sequential order such that like terms of the m second polynomials in base 2n are lined up and added to generate and store the final product having 2m digits in base 2n in the second register unit;
• wherein each polynomial adder comprises a m-bit adder and n half adders in a carry-chained configuration;
• and
• wherein each of the multiplicand and the multiplier has m digits in base 2n and both n and m are integers greater than 0.

An operating method of an in-memory multiplication device that performs multiplication on a multiplicand and a multiplier to generate a final product, the in-memory multiplication device comprising a number m2 of in-memory multiplier units, a number m of binary adder devices, a register unit and zero or a number (m−1) of polynomial adders, the method comprising the steps of:

• comparing a first n-bit digit and a second n-bit digit respectively selected from the multiplicand and the multiplier with a number 22n of 2n-bit operand symbols hardwired in a first read-only-memory (ROM) array to output one of a number 22n of 2n-bit response symbols hardwired in a second ROM array as a 2n-bit product code by each in-memory multiplier unit comprising the first ROM array and the second ROM array so that a number m2 of 2n-bit product codes are outputted in parallel from the number m2 of in-memory multiplier units, wherein the number m2 of 2n-bit product codes serve as first coefficients of a number m of first polynomials in base 2n and the first coefficients of each first polynomial in base 2n are associated with multiplication of the multiplicand with a corresponding digit of the multiplier;
• when m>=2, sequentially adding a most significant digit of the first coefficient of a less degree term and a least significant digit of the first coefficient of a larger degree term adjacent to the less degree term for each first polynomial in ascending degree by each binary adder device comprising (m−1) n-bit adders and n half adders in a carry-chained configuration so that the 2n-bit first coefficients of the m first polynomials in base 2n are converted into n-bit second coefficients of m second polynomials in base 2n in parallel by the m binary adder devices;
• and
• when m>=2, sequentially adding the m second polynomials in base 2n in ascending degrees by the number (m−1) of polynomial adders arranged in sequential order such that like terms of the m second polynomials in base 2n are lined up and added to generate and store a final product having 2m digits in base 2n in the register unit, wherein each polynomial adder comprises a (m×n)-bit adder and n half adders in a carry-chained configuration;
• wherein the number m2 of in-memory multiplier units and the number m of binary adder devices are respectively arranged in a parallel configuration and each of the multiplicand and the multiplier has m digits in base 2n and both n and m are integers greater than 0.