Multi-core audio processor with deadline scheduler

A multi-core audio processor comprising:

• a plurality of audio processing cores having differing capabilities;
• a plurality of deadline registers configured to store a plurality of deadline values indicating an ordering of processing of a plurality of audio streams by the plurality of audio processing cores, wherein a deadline scheduler is configured to update at least one of the plurality of deadline values per clock cycle;
• and
• a plurality of audio processing core interfaces communicably coupling the plurality of audio processing cores to a stream prioritization circuit, wherein each audio processing core interface is associated with a corresponding audio processing core,
• wherein the stream prioritization circuit comprises a plurality of compare trees, each compare tree configured to instruct a corresponding audio processing core to service an audio stream based on the plurality of deadline values via a corresponding audio processing core interface.

A multi-core audio processor comprising:

• a plurality of audio processing cores having different processing capabilities, at least one of the audio processing cores configured to perform block data processing and at least one of the audio processing cores configured to perform single sample data processing;
• an audio transport block including a first plurality of audio interfaces configured to communicate data of a first plurality of audio channels and a second plurality of audio interfaces configured to communicate data of a second plurality of channels;
• a first plurality of buffers, at least one of the first plurality of buffers associated with each of the first plurality of audio interfaces, the processor configurable to synchronously store data of the first plurality of audio channels in the first plurality of buffers as a first audio stream;
• a second plurality of buffers, at least one of the second plurality of buffers associated with each of the second plurality of audio interfaces, the processor configurable to synchronously store data of the second plurality of audio channels in the second plurality of buffers as a second audio stream;
• and
• a deadline scheduler including a first deadline register configured to store a first deadline value for a first processing task associated with the first audio stream and a second deadline register configured to store a second deadline value for a second processing task associated with the second audio stream, the processor configured to update an order in which the first and second processing tasks are performed based on based on amounts of data stored in the first and second pluralities of buffers.