US 11,457,524 B2 · Integrated filter for de-sense reduction

Abstract

A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.

Claims11

Dependent claims

A chip package, comprising:

at least one signal pin;
a filter including a plurality of ground pins,
wherein the at least one signal pin is configured to carry a signal that conforms to an interface protocol;
and
wherein the plurality of ground pins at least partially surround the at least one signal pin,
wherein the plurality of ground pins are configured to filter electromagnetic interference generated by the signal to be carried by the at least one signal pin;
and
an electrostatic discharge circuit electrically connected to one or more of the ground pins;
wherein the electrostatic discharge circuit includes a plurality of diodes arranged in a symmetric pattern relative to the at least one signal pin.

6 more elements

Dependencies are inferred from the claim text.

Integrated filter for de-sense reduction

Life of this patent

Integrated filter for de-sense reduction

Life of this patent

Abstract

Claims11