Radio communications

A non-transitory, computer readable medium comprising instructions that, when executed on a suitable processor, performs a method of operating a radio receiver device, the radio receiver device comprising:

• an indexed memory portion having a length of at least A+B+C memory units, wherein A, B, and C are positive, non-zero integers, and wherein the radio receiver device is arranged to receive a plurality of data symbols from an incoming bitstream and store a plurality of samples of each of the plurality of data symbols in the indexed memory portion, said indexed memory portion being logically arranged such that:
• a first data buffer has an initial address at an index 0 and a final address at an index A−1;
• a timing adjustment buffer has an initial address at an index A and a final address at an index A+B−1;
• a second data buffer has an initial address at index an A+B and a final address at an index A+B+C−1;
• and
• a buffer switch pointer having a trigger address and arranged to trigger a switch from the first data buffer to the second data buffer when a current address matches the trigger address, said trigger address being an address between the index 0 and the index A+B−1;
• wherein the method comprises:
• setting the current address to the index 0 on initialisation;
• storing each of the plurality of samples at the current address;
• incrementing the current address if the current address does not match the trigger address, but setting the current address to an index A+B if the current address does match the trigger address;
• and
• determining when there is a timing offset between a local reference clock and a network clock and moving the trigger address in order to reduce the timing offset.

A radio receiver device comprising:

• an indexed memory portion, wherein the radio receiver device is arranged to receive a plurality of data symbols from an incoming bitstream and store a plurality of samples of each of the plurality of data symbols in the indexed memory portion, said indexed memory portion being logically arranged such that the indexed memory portion comprises a plurality of pairs of data buffers and timing adjustment buffers, wherein each pair is of length A+B memory units, where A and B are non-zero, positive integers, each comprising:
• a data buffer having an initial address at an index 0 and a final address at an index A−1;
• a timing adjustment buffer having an initial address at an index A and a final address at an index A+B−1;
• and
• a buffer switch pointer having a trigger address and arranged to trigger when a current address matches the trigger address, said trigger address being an address between the index 0 and the index A+B−1;
• wherein the radio receiver device is arranged such that:
• on initialisation, the current address is set to the index 0;
• each of the plurality of samples is stored at the current address;
• if the current address does not match the trigger address, the current address is incremented, but if the current address does match the trigger address, the current address is set to the index 0 of a data buffer within a different pair;
• and
• if the radio receiver device determines that there is a timing offset between a local reference clock and a network clock, the trigger address is moved in order to reduce the timing offset.