Methods and arrangements to accelerate array searches

A method, comprising:

• comparing, by a search acceleration logic circuitry, a first incoming packet of the incoming packets to a digest of a first entry in a primary array to determine whether the first incoming packet matches the digest of the first entry;
• when the first incoming packet matches the digest of the first entry in the primary array, retrieving, by the search acceleration logic circuitry, a first full entry from a secondary array, the first full entry to correspond to the first entry, and comparing the first full entry with the first incoming packet;
• when the first full entry matches the first incoming packet, storing, by the search acceleration logic circuitry, at least a portion of the first incoming packet at a first memory location;
• and
• in absence of a match between the first incoming packet and the first digest or the first full entry, comparing, by the search acceleration logic circuitry, the first incoming packet to subsequent entries in a primary array of entries and the secondary array of entries to identify a full entry in the secondary array of entries that matches the first incoming packet.

A system comprising:

• a memory;
• one or more network interface ports coupled with the memory to store incoming packets in the memory;
• search acceleration logic circuitry coupled with the memory to compare a first incoming packet to a first digest in a first entry of a primary array to determine whether the first incoming packet matches the first digest;
• when the first incoming packet matches the first digest, the search acceleration logic circuitry to retrieve a first full entry from a secondary array, the first full entry to correspond to the first entry, and to compare the first full entry with the first incoming packet;
• when the first full entry matches the first incoming packet, the search acceleration logic circuitry to store at least a portion of the first incoming packet at a first memory location, wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets;
• and
• in absence of a match between the first incoming packet and the first digest or between the first incoming packet and the first full entry, the logic circuitry to compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

A non-transitory machine-readable medium containing instructions, which when executed by a processor, cause the processor to perform operations, the operations comprising:

• comparing a first incoming packet of the incoming packets to a digest of a first entry in a primary array to determine whether the first incoming packet matches the digest of the first entry;
• when the first incoming packet matches the digest of the first entry in the primary array, retrieving a first full entry from a secondary array, the first full entry to correspond to the first entry, and comparing the first full entry with the first incoming packet;
• when the first full entry matches the first incoming packet, storing at least a portion of the first incoming packet at a first memory location;
• and
• in absence of a match between the first incoming packet and the first digest or the first full entry, comparing the first incoming packet to subsequent entries in the primary array of entries and the secondary array of entries to identify a full entry in the secondary array of entries that matches the first incoming packet.