Joint linear delay and phase compensation for multiple antenna branches

A phase and delay compensation system configured to compensate for phase and delay introduced by each of a plurality of transmitter circuits in one of a network node and a wireless device, the system comprising processing circuitry configured to:

• generate N signals xp from N frequency domain signals Xp, N being an integer greater than 1, each frequency domain signal Xp being an Nf point Fourier transform of a corresponding signal xp, each frequency domain signal Xp having components being assigned to Mp different frequency bins, Mp being an integer greater than 2, each signal xp having an orthogonal frequency division multiplex (OFDM), symbol and cyclic prefix (CP);
• inject each signal xp into a different one of N parallel feed forward paths, each parallel feed forward path having a phase/delay compensation circuit and a transmitter circuit, each phase/delay compensation circuit configured to introduce a different amount of first phase and first delay to a respective signal xp to produce a signal zp, each transmitter circuit (104) introducing a different amount of unknown phase θp and unknown delay Dp to a respective signal zp, so that each transmitter circuit outputs a different output signal yp;
• apply an Nf point Fourier transform to a sum of the output signals yp;
• split the Fourier transformed sum to produce N signals Yp,
• input each signal Yp to a different one of N parallel feedback paths, each parallel feedback path having a phase/delay compensation replica circuit corresponding to a phase/delay compensation circuit and configured to introduce a corresponding first phase and first delay to a respective signal Yp to produce a signal Yp′;
• apply an Nf point Fourier transform to each signal zp to produce a signal Zp;
• input each of the N signals Yp′ and a corresponding one of the N signals Zp to a least squared process to produce N corrective signals vp;
• and
• adjust each phase/delay compensation circuit by a respective one of the N corrective signals vp to compensate for the unknown phase θp and unknown delay Dp introduced by each transmitter circuit of the plurality of parallel transmitter circuits in the plurality of feed forward paths.

A phase and delay compensation system implemented in a network node configured to compensate for phase and delay introduced by each of a plurality of parallel transmitter circuits, the system comprising processing circuitry configured to:

• inject N signals, x, into N circuit paths that each include a phase/delay compensation module and a transmitter circuit, N being an integer greater than 1, each signal x having an orthogonal frequency division multiplex (OFDM), symbol and cyclic prefix (CP), x being generated by an Nf point inverse Fourier transform on a frequency domain signal X, each frequency domain signal X having components being assigned to M different frequency bins, M being an integer greater than 2;
• introduce to each of the N signals x a first phase and a first delay via a phase/delay compensation module to produce from each of the N circuit paths an output signal z;
• input each of the N signals z to a different transmitter circuit, which introduces to the signal z an unknown phase and an unknown delay to produce one of N outputs y;
• sum by an adder the N outputs y to form a sum signal;
• perform an Nf point Fourier transform, via an FFT, on the sum signal to produce a Fourier transformed output signal;
• split the Fourier transformed output signal, via a splitter, into N parallel signals Y, each signal Y having components from different ones of the M frequency bins;
• introduce to each of the N signals Y the first phase and first delay in a phase/delay compensation replica module to produce N corresponding signals Y′;
• perform an Nf point Fourier transform, via an FFT, on each signal z to produce a plurality of N parallel signals Z;
• input each of the N signals Y′ and a corresponding one of the N signals Z to a least squared process to produce N corrective signals v;
• and
• adjust each phase/delay compensation module by a respective one of the N corrective signals v to compensate for the unknown phase and unknown delay introduced by each transmitter circuit in the plurality of parallel transmitter circuits.

A method of compensating for phase and delay introduced by each of a plurality of transmitter circuits, the method comprising:

• generating a plurality of test signals x, each test signal x having frequency components distributed over a plurality of frequency bins;
• injecting each of the plurality of test signals x into a different one of a plurality of branches, each branch having a phase/delay compensation circuit and a transmitter circuit, each phase/delay compensation circuit having a first phase and first delay applied to a test signal x to produce a signal z and the transmitter circuit configured to receive the signal z and having an unknown phase and unknown delay applied to the signal z to produce an output signal y;
• converting the output signals y from the plurality of branches to a frequency domain to produce a first set of frequency domain signals Y, each frequency domain signal Y having frequency components distributed over the plurality of frequency bins;
• converting the signals z to the frequency domain to produce a second set of frequency domain signals Z, each frequency domain signal Z corresponding to a frequency domain signal Y;
• applying the first phase and first delay to each signal Y via a phase/delay compensation replica circuit to produce a signal Y′;
• comparing each signal Y′ to a corresponding signal Z to produce a corrective signal v;
• and
• applying the corrective signal v to a corresponding phase/delay compensation circuit in a branch to compensate for the unknown phase and unknown delay of a corresponding transmitter circuit in the branch.