Cryptography method and circuit, corresponding device

A circuit, comprising:

• an input node configured to receive, from a microcontroller and over a communication bus, access requests to memory locations, said memory locations being accessible via said communication bus, wherein said access requests including burst requests for access to respective sets of said memory locations starting from respective start addresses, the burst requests conveying said respective start addresses;
• a security node coupled to the microcontroller and configured to receive a security mode signal indicative of a security status of the microcontroller;
• an output node configured to transmit over said communication bus output data;
• and
• processing circuitry coupled to said input node, said security node and said output node and configured to enable processing of received access requests based on the security mode signal, wherein processing of a received access request includes:
• calculating, as a function of said start addresses, encryption or decryption cryptographic masks based on cryptographic keys;
• receiving plain text data for encryption or encrypted data stored in said memory locations;
• applying said cryptographic masks as a function of a value of the security mode signal:
• to encrypt said plain text data, generating encrypted data;
• or
• to decrypt encrypted data stored in said memory locations, generating decrypted data;
• and
• including said encrypted data or said decrypted data into output data provided on said output node for transmission over said communication bus.

A device, comprising:

• memory locations configured to store encrypted data, said memory locations having respective addresses;
• a communication bus coupled to the memory locations and configured to convey access requests to said memory locations, wherein said access requests include burst requests for access to respective sets of said memory locations starting from respective start addresses, the burst requests conveying said respective start addresses, the access requests being from a microcontroller;
• and
• a circuit coupled to said communication bus and to the microcontroller and having:
• an input node configured to receive over said communication bus access requests to said memory locations, wherein the access requests include burst requests for access to respective sets of said memory locations starting from respective start addresses, the burst requests conveying said respective start addresses,
• a security node configured to receive a security mode signal indicative of a security mode of the microcontroller, wherein the circuit is configured to enable processing of access requests based on the security mode signal, and
• an output node configured to transmit over said communication bus output data, wherein, in response to the processing of access requests being enable, the circuit is configured to calculate, as a function of said start addresses, encryption and decryption cryptographic masks based on cryptographic keys and to receive plain text data for encryption or encrypted data stored in said memory locations, and to apply said cryptographic masks to encrypt said plain text data to obtain encrypted data or to decrypt encrypted data stored in said memory locations to obtain therefrom decrypted data as a function of a value of a secure mode signal, and to include said encrypted data or said decrypted data in output data provided on said output node.