Phase interpolation based clock data recovery circuit and communication device including the same

A communication device comprising:

• a clock data recovery circuit configured to receive an input data signal provided through a communication channel,
• wherein the clock data recovery circuit includes:
• a phase locked loop (PLL) configured to generate a plurality of reference clock signals of which frequencies are modulated based on a first start signal, each of the plurality of reference clock signals having a first profile that is periodically fluctuated;
• a code signal generator configured to generate a first compensation code signal based on a second start signal, the first compensation code signal having a second profile that is periodically fluctuated and is different from the first profile;
• and
• a clock and data generator configured to generate a recovered data signal by sampling the input data signal according to a clock signal, and to compensate a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and
• wherein the clock and data generator includes a phase interpolator configured to generate the clock signal based on the plurality of reference clock signals and the first compensation code signal.

A clock data recovery circuit based on phase interpolation comprising:

• a phase locked loop (PLL) configured to generate a plurality of reference clock signals of which frequencies are modulated based on a first start signal, each of the plurality of reference clock signals having a first profile that is periodically fluctuated;
• a code signal generator configured to generate a first compensation code signal based on a second start signal, the first compensation code signal having a second profile that is periodically fluctuated and is different from the first profile;
• and
• a clock and data generator configured to generate a recovered data signal by sampling an input data signal based on a clock signal,
• wherein the code signal generator includes:
• a table configured to store raw data used to generate the first compensation code signal;
• and
• a table accumulator configured to generate the first compensation code signal based on the second start signal and the raw data,
• wherein the clock and data generator includes:
• a phase detector configured to generate an up signal and a down signal representing a phase difference between the input data signal and the clock signal;
• a filtering circuit configured to generate a control code signal based on the up signal and the down signal;
• an adder configured to sum the control code signal and the first compensation code signal;
• and
• a phase interpolator configured to generate the clock signal based on the plurality of reference clock signals and an output of the adder,
• wherein the phase interpolator is configured to compensate a first frequency modulation on the plurality of reference clock signals based on the output of the adder,
• wherein the first profile corresponds to a second frequency modulation with a first triangular waveform, and has a first waveform that is regularly repeated for each unit interval,
• the second profile corresponds to a third frequency modulation with a second triangular waveform, and has a second waveform this is regularly repeated for each unit interval,
• wherein the first profile and the second profile have opposite shapes,
• wherein the first waveform increases with a first slope in a first interval of the unit interval and decreases with a second slope in a second interval of the unit interval, and
• wherein the second waveform decreases with the second slope in the first interval and increases with the first slope in the second interval.