Asynchronous sampling architecture and chip
AssigneeShenzhen Goodix Technology Co., Ltd.
InventorsWen-Chi Wang, Hsin-Min Wang, Ju-Chieh Liu
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Abstract
The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.
Claims16
An asynchronous sampling architecture, configured to receive a first input data string from a peer end, wherein the asynchronous sampling architecture comprises:
- a first register, configured to buffer the first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end;
- and
- a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out from the first register as a first output data string according to the gated clock;
- wherein the gated clock generation unit generates the gated clock according to a first frequency difference between the peer end clock and a local clock of the asynchronous sampling architecture, a pre-determined margin for frequency rise, the local clock and an asynchronous sampling rate conversion clock, wherein the frequency of the asynchronous sampling rate conversion clock is greater than the frequency of the local clock, and a second frequency difference between the frequency of the asynchronous sampling rate conversion clock and the frequency of the local clock is the product of the frequency the local clock and the pre-determined margin for frequency rise.
An asynchronous sampling architecture, configured to receive a first input data string from a peer end, wherein the asynchronous sampling architecture comprises:
- a first register, configured to buffer the first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end;
- and
- a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out from the first register as a first output data string according to the gated clock, wherein the gated clock generation unit generates the gated clock according to a first frequency difference between the peer end clock and a local clock of the asynchronous sampling architecture;
- a frequency difference estimation unit, configured to estimate the first frequency difference according to an amount of storage used in the first register, wherein the frequency difference estimation unit estimates the first frequency difference according to the amount of storage used in the first register and the local clock;
- wherein the frequency difference estimation unit obtains a storage change in the first register within a pre-determined period according to the local clock, and estimates the first frequency difference according to the pre-determined period and the storage change.
An asynchronous sampling architecture, configured to receive a first input data string from a peer end, wherein the asynchronous sampling architecture comprises:
- a first register, configured to buffer the first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end;
- and
- a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out from the first register as a first output data string according to the gated clock;
- and
- a second register, configured to buffer a second input data string, wherein the second input data string is written into the second register according to the gated clock, the second input data string is read from the second register as a second output data string according to the peer end clock, and the peer end receives the second output data string from the asynchronous sampling architecture.
Dependencies are inferred from the claim text.