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AssigneeMitsubishi Electric Corporation
InventorsYuta Takemoto, Akinori Fujimura, Yuichi Yamamoto
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A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.
A demultiplexing circuit, which is capable of demultiplexing a reception signal into a plurality of signals, the demultiplexing circuit comprising a multi-stage demultiplexing circuit in which frequency shift decimator circuits are connected in a plurality of stages in a tree format,
A multiplexing circuit, which is configured to multiplex a plurality of input signals, the multiplexing circuit comprising a multi-stage multiplexing circuit in which frequency interpolator circuits are connected in a plurality of stages in a tournament format,
Dependencies are inferred from the claim text.