US 11,456,758 B1 · Adaptive soft-bit compression in flash memory

Abstract

A memory includes, in one embodiment, NAND elements; read/write circuitry; and compressed soft-bit circuitry. The compressed soft-bit circuitry is configured to determine or receive one or more NAND conditions and then determine a soft-bit delta and select a compression scheme based on the NAND conditions. The read/write circuitry is configured to read a set of hard bits from the NAND elements and sense a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the NAND elements. The first set of soft-bits has a first fixed size, and each soft-bit of the first set of soft-bits indicates a reliability of a corresponding hard bit of the set of hard bits. The compressed soft-bit circuitry is also configured to generate a second set of soft-bits based on the selected compression scheme and output the second set of soft-bits to a controller.

Claims20

Dependent claims

A memory, comprising:

one or more storage elements;
compressed soft-bit circuitry configured to:
determine a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of the one or more storage elements;
read/write circuitry configured to:
read a set of hard bits from the one or more storage elements, and
sense a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits,
wherein the compressed soft-bit circuitry is further configured to:
receive the first set of soft-bits,
generate a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined, and
output the second set of soft-bits.

7 more elements

A method comprising:

determining, with compressed soft-bit circuitry, a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of one or more storage elements;
reading, with read/write circuitry, a set of hard bits from the one or more storage elements;
sensing, with the compressed soft-bit circuitry, a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits;
receiving, with the compressed soft-bit circuitry, the first set of soft-bits;
generating, with the compressed soft-bit circuitry, a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined;
and
outputting the second set of soft-bits.

4 more elements

An apparatus comprising:

means for determining a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of one or more storage elements;
means for reading a set of hard bits from the one or more storage elements;
means for sensing a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits;
means for receiving the first set of soft-bits;
means for generating a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined;
and
means for outputting the second set of soft-bits.

4 more elements

Dependencies are inferred from the claim text.

Adaptive soft-bit compression in flash memory

Life of this patent

Adaptive soft-bit compression in flash memory

Life of this patent

Abstract

Claims20