Oscillation detection and mitigation in bit-flipping decoders

A system for improving a decoding performance of a bit-flipping decoder associated with a non-volatile memory, comprising:

• a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause the processor to:
• receive a noisy codeword that is based on a transmitted codeword generated from an irregular quasi-cyclic low-density parity-check (QC-LDPC) code;
• perform a first plurality of decoding iterations on the noisy codeword, at least one of the first plurality of decoding iterations comprising performing a message passing algorithm in a first order;
• compute, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations;
• determine that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold (T);
• and
• perform a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

A non-transitory computer-readable storage medium having instructions stored thereupon for improving a decoding performance of a bit-flipping decoder associated with a non-volatile memory, comprising:

• instructions for receiving a noisy codeword that is based on a transmitted codeword generated from a quasi-cyclic low-density parity-check (QC-LDPC) code;
• instructions for performing a first plurality of decoding iterations on the noisy codeword, at least one of the first plurality of decoding iterations comprising performing a message passing algorithm in a first order;
• instructions for computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations;
• instructions for determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold (17);
• and
• instructions for performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.