US 11,456,756 B2Granted

Transmission device, transmission method, reception device, and reception method

AssigneeSony Corporation

InventorsMakiko Yamamoto, Yuji Shinohara

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Abstract

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 5/16, 6/16, or 7/16. The parity check matrix includes an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of M1 rows and M1 columns having a step structure, a Z matrix being a zero matrix of M1 rows and N−K−M1 columns, a C matrix of N−K−M1 rows and K+M1 columns, and a D matrix being an identity matrix of N−K−M1 rows and N−K−M1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns. The present technology can be applied to, for example, data transmission using an LDPC code.

Claims4

Dependent claims

A transmission device comprising:

processing circuitry configured to
perform LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 5/16 to generate a transmission signal for transmission;
and
transmit the transmission signal, wherein
the parity check matrix includes
an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, the A matrix being an upper left matrix of the parity check matrix,
a B matrix of M1 rows and M1 columns, the B matrix having a step structure adjacent to right of the A matrix,
a Z matrix of M1 rows and N−K−M1 columns, the Z matrix being a zero matrix adjacent to right of the B matrix,
a C matrix of N−K−M1 rows and K+M1 columns, the C matrix being adjacent to below the A matrix and the B matrix, and
a D matrix of N−K−M1 rows and N−K−M1 columns, the D matrix being an identity matrix adjacent to right of the C matrix,
the predetermined value M1 is 720,
the A matrix and the C matrix are represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, and is
301 342 350 1797 7970 8230 10820 11305
139 530 615 1566 6290 6425 9185 9466
48 419 444 1773 3213 4793 8594 10480
246 455 531 3011 5845 7383 8393 10709
39 262 290 3282 5208 9539 10955 11204
234 267 623 1033 1537 8766 11527 11557
494 661 671 1123 4497 6601 6715 10473
164 425 436 3259 4505 5614 8192 10221
326 377 477 7699 10162 11174 11878
206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549
402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398
39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879
639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518
337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254
32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173
910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863
790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498.

27 more elements

A transmission method comprising:

performing, by processing circuitry, LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 5/16 to generate a transmission signal for transmission;
and
transmitting, to a reception device, the transmission signal, wherein
the parity check matrix includes
an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, the A matrix being an upper left matrix of the parity check matrix,
a B matrix of M1 rows and M1 columns, the B matrix having a step structure adjacent to right of the A matrix,
a Z matrix of M1 rows and N−K−M1 columns, the Z matrix being a zero matrix adjacent to right of the B matrix,
a C matrix of N−K−M1 rows and K+M1 columns, the C matrix being adjacent to below the A matrix and the B matrix, and
a D matrix of N−K−M1 rows and N−K−M1 columns, the D matrix being an identity matrix adjacent to right of the C matrix,
the predetermined value M1 is 720,
the A matrix and the C matrix are represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, and is
301 342 350 1797 7970 8230 10820 11305
139 530 615 1566 6290 6425 9185 9466
48 419 444 1773 3213 4793 8594 10480
246 455 531 3011 5845 7383 8393 10709
39 262 290 3282 5208 9539 10955 11204
234 267 623 1033 1537 8766 11527 11557
494 661 671 1123 4497 6601 6715 10473
164 425 436 3259 4505 5614 8192 10221
326 377 477 7699 10162 11174 11878
206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549
402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398
39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879
639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518
337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254
32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173
910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863
790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498.

26 more elements

A reception device comprising:

processing circuitry configured to
receive a transmission signal including an LDPC code;
and
decode the LDPC code with a code length N of 17280 bits and a coding rate r of 5/16, the LDPC code being obtained from the transmission signal that is generated based on LDPC coding being performed on a basis of a parity check matrix of the LDPC code, wherein
the parity check matrix includes
an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, the A matrix being an upper left matrix of the parity check matrix,
a B matrix of M1 rows and M1 columns, the B matrix having a step structure adjacent to right of the A matrix,
a Z matrix of M1 rows and N−K−M1 columns, the Z matrix being a zero matrix adjacent to right of the B matrix,
a C matrix of N−K−M1 rows and K+M1 columns, the C matrix being adjacent to below the A matrix and the B matrix, and
a D matrix of N−K−M1 rows and N−K−M1 columns, the D matrix being an identity matrix adjacent to right of the C matrix,
the predetermined value M1 is 720,
the A matrix and the C matrix are represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, and is
301 342 350 1797 7970 8230 10820 11305
139 530 615 1566 6290 6425 9185 9466
48 419 444 1773 3213 4793 8594 10480
246 455 531 3011 5845 7383 8393 10709
39 262 290 3282 5208 9539 10955 11204
234 267 623 1033 1537 8766 11527 11557
494 661 671 1123 4497 6601 6715 10473
164 425 436 3259 4505 5614 8192 10221
326 377 477 7699 10162 11174 11878
206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549
402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398
39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879
639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518
337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254
32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173
910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863
790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498.

27 more elements

A reception method comprising:

receiving, by processing circuitry from a transmission device, a transmission signal including an LDPC code;
and
decoding the LDPC code with a code length N of 17280 bits and a coding rate r of 5/16, the LDPC code being obtained from the transmission signal that is generated based on LDPC coding being performed on a basis of a parity check matrix of the LDPC code, wherein
the parity check matrix includes
an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, the A matrix being an upper left matrix of the parity check matrix,
a B matrix of M1 rows and M1 columns, the B matrix having a step structure adjacent to right of the A matrix,
a Z matrix of M1 rows and N−K−M1 columns, the Z matrix being a zero matrix adjacent to right of the B matrix,
a C matrix of N−K−M1 rows and K+M1 columns, the C matrix being adjacent to below the A matrix and the B matrix, and
a D matrix of N−K−M1 rows and N−K−M1 columns, the D matrix being an identity matrix adjacent to right of the C matrix,
the predetermined value M1 is 720,
the A matrix and the C matrix are represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, and is
301 342 350 1797 7970 8230 10820 11305
139 530 615 1566 6290 6425 9185 9466
48 419 444 1773 3213 4793 8594 10480
246 455 531 3011 5845 7383 8393 10709
39 262 290 3282 5208 9539 10955 11204
234 267 623 1033 1537 8766 11527 11557
494 661 671 1123 4497 6601 6715 10473
164 425 436 3259 4505 5614 8192 10221
326 377 477 7699 10162 11174 11878
206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549
402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398
39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879
639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518
337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254
32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173
910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863
790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498.

26 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/757,911Filed 17 Oct 2018
Priority: JP JP2017-20987431 Oct 2017
Published: US 2020/0343910 A129 Oct 2020
Granted: 27 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03M 13/036
Theoretical methods to calculate these checking codes: heuristic code construction methods, i.e. code construction or code search based on using…
H03M 13/1102
Using multiple parity bits: codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/1165
Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices: qC-LDPC codes as defined…
H03M 13/255
Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded…: with…