Phase-locked loop circuit having linear voltage-domain time-to-digital converter with output subrange
AssigneeMediatek Inc.
InventorsAng-Sheng Lin, Chun-Wei Chang, Tzu-Chan Chueh
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AssigneeMediatek Inc.
InventorsAng-Sheng Lin, Chun-Wei Chang, Tzu-Chan Chueh
Estimating the term…
A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
A phase-locked loop (PLL) circuit, comprising:
A sub-range controlling circuit to be disposed between a charge pump and an analog-to-digital converter (ADC) in a phase-locked loop (PLL) circuit, comprising:
A method of a phase-locked loop (PLL) circuit, comprising:
Dependencies are inferred from the claim text.