Timing margin detecting circuit, timing margin detecting method and clock and data recovery system

A timing margin detecting method, applied in a timing margin detecting circuit coupled to a clock and data recovery (CDR) circuit, the method comprising:

• receiving a first data signal and a first clock signal and generating a second data signal and a second clock signal according to a control signal, the first data signal and the first clock signal, wherein the second clock signal has a delay relative to the second data signal;
• generating a sampled data signal according to the second data signal and the second clock signal;
• determining whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly, wherein the determination result is a first logic value, indicating that the sampled data signal is the same as the predefined test pattern or a second logic value opposite to the first logic value, indicating that the sampled data signal is not the same as the predefined test pattern;
• determining a timing margin corresponding to a configuration of the CDR circuit that makes the CDR circuit operate in a corresponding bandwidth;
• determining the timing margin according to a plurality of determination results corresponding to a plurality of delays;
• adjusting the configuration of the CDR circuit to determine an another timing margin;
• and
• determining the timing margin according to a first delay and a second delay when a first determination result corresponding to the first delay, a second determination result corresponding to the second delay and a third determination result corresponding to a third delay are obtained, wherein the first determination result and the second determination result indicate that the sampled data signal is not the same as the predefined test pattern, and the third determination result indicates that the sampled data signal is the same as the predefined test pattern;
• wherein the third delay is larger than the first delay and smaller than the second delay.

A clock and data recovery (CDR) system, comprising:

• a CDR circuit;
• and
• a timing margin detecting circuit, coupled to the CDR circuit, comprising:
• a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal according to a control signal, the first data signal and the first clock, wherein the second clock signal has a delay relative to the second data signal;
• a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal and determine a timing margin corresponding to a configuration of the CDR circuit that makes the CDR circuit operate in a corresponding bandwidth;
• a first sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal;
• and
• a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly, wherein the determination result is a first logic value, indicating that the sampled data signal is the same as the predefined test pattern or a second logic value opposite to the first logic value, indicating that the sampled data signal is not the same as the predefined test pattern;
• wherein the controller determines the timing margin according to a plurality of determination results that the bit error rate determination circuit generates corresponding to a plurality of delays, and the controller adjusts the configuration of the CDR circuit to determine an another timing margin;
• wherein the controller obtains a first determination result corresponding to a first delay and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern;
• the controller obtains a second determination result corresponding to a second delay and the second determination result indicates that the sampled data signal is not the same as the predefined test pattern;
• the controller obtains a third determination result corresponding to a third delay and the third determination result indicates that the sampled data signal is the same as the predefined test pattern, the third delay is larger than the first delay and smaller than the second delay;
• and the controller determines the timing margin according to the first delay corresponding to the first determination result and the second delay corresponding to the second determination result.