Normally-off power switch with integrated failsafe pulldown circuit and controllable turn-off time

A semiconductor die, comprising:

• a control terminal;
• a first reference terminal;
• a normally-off power transistor having a gate electrically connected to the control terminal;
• and
• a first failsafe pulldown circuit comprising:
• a first normally-on pulldown transistor having a gate electrically connected to the first reference terminal, wherein the first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal;
• and
• a first resistor electrically connected in series between the first normally-on pulldown transistor and the gate of the normally-off power transistor.

A semiconductor device, comprising:

• a normally-off power transistor integrated in a semiconductor die, wherein a gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die;
• and
• a first failsafe pulldown circuit comprising:
• a first normally-on pulldown transistor integrated in the semiconductor die, wherein a gate of the first normally-on pulldown transistor is electrically connected to a first reference terminal of the semiconductor die, wherein the first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal;
• and
• a turn-off time control circuit configured to control a turn-off time of the normally-off power transistor,
• wherein the first failsafe pulldown circuit further comprises a pulldown control circuit connected between the gate of the first normally-on pulldown transistor and a source of the first normally-on pulldown transistor,
• wherein the pulldown control circuit is configured to autonomously apply a negative voltage to the gate of the first normally-on pulldown transistor, relative to the source of the first normally-on pulldown transistor, when a turn-on voltage is applied between the control terminal and the first reference terminal, and to autonomously discharge the negative voltage when the turn-on voltage is not applied between the control terminal and the first reference terminal.

A semiconductor device, comprising:

• a normally-off power transistor integrated in a semiconductor die, wherein a gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die;
• a first failsafe pulldown circuit comprising:
• a first normally-on pulldown transistor integrated in the semiconductor die, wherein a gate of the first normally-on pulldown transistor is electrically connected to a first reference terminal of the semiconductor die, wherein the first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal;
• and
• a turn-off time control circuit configured to control a turn-off time of the normally-off power transistor;
• and
• a second failsafe pulldown circuit configured to pull down the gate of the normally-off power transistor to a voltage below the threshold voltage of the normally-off power transistor when the normally-off power transistor is in a powered down state during which no switching of the normally-off power transistor occurs.