Comparator

A comparator, comprising:

• a first stage circuit, configured to receive a voltage signal to be compared and a reference voltage signal, and to generate and output a first amplifying signal and a second amplifying signal based on the voltage signal to be compared and the reference voltage signal;
• a second stage circuit, connected with the first stage circuit, configured to generate and latch a first output signal and a second output signal based on the first amplifying signal and the second amplifying signal;
• wherein at least one of the first stage circuit and the second stage circuit comprises a first pair of cross-coupled transistors;
• wherein the first stage circuit comprises:
• a transistor M0, having a source connected with a high voltage source and a gate connected with a clock signal;
• a transistor M1, having a source connected with a drain of the transistor M0, a drain connected with the second stage circuit to transmit the first amplifying signal to the second stage circuit, and a gate connected with the voltage signal to be compared;
• a transistor M2, having a source connected with the drain of the transistor M0, a drain connected with the second stage circuit to transmit the second amplifying signal to the second stage circuit, and a gate connected with the reference voltage signal;
• a transistor M3, having a source connected with a low voltage source, a gate and a drain of the transistor M3 are connected with each other and commonly connected to the drain of transistor M1;
• a transistor M4, having a source connected with the low voltage source, a gate and a drain of the transistor M4 are connected with each other and commonly connected to the drain of the transistor M2;
• a transistor M12, having a source connected with the drain of the transistor M0, a drain connected with the drain of the transistor M1, and a gate connected with the drain of the transistor M2;
• and
• a transistor M13, having a source connected with the drain of the transistor M0, a drain connected with the drain of the transistor M2, and a gate connected with the drain of the transistor M1.