Data retention circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Chi Huang, Yung-Chen Chien, Chi-Lin Liu, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
Life of this patent
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Abstract
A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.
Claims20
A circuit comprising:
- a first power domain having a first power supply voltage level, the first power domain comprising:
- a master latch;
- a first level shifter;
- and
- a slave latch coupled between the master latch and the first level shifter;
- and
- a second power domain having a second power supply voltage level different from the first power supply voltage level, the second power domain comprising a retention latch coupled between the slave latch and the first level shifter,
- wherein the retention latch comprises a second level shifter.
An integrated circuit (IC) comprising:
- a master latch;
- a first level shifter;
- a slave latch electrically coupled between the master latch and the first level shifter;
- and
- a retention latch comprising a second level shifter and electrically coupled between the slave latch and the first level shifter,
- wherein
- each of the slave latch, the master latch, and the first level shifter comprises portions of each of a first power node and a first n-well,
- the retention latch comprises portions of each of a second power node and a second n-well separate from the first n-well, and
- the first power node is configured to have a first power supply voltage level different from a second power supply voltage level of the second power node.
A method of retaining a data bit, the method comprising:
- outputting a first logic level from a slave latch in a first power domain;
- receiving the first logic level at a retention latch in a second power domain;
- using a first level shifter in the retention latch to generate a complementary bit pair based on the first logic level;
- and
- using a second level shifter in the first power domain to output a second logic level to the slave latch, the second logic level being based on the complementary bit pair,
- wherein the first power domain has a first power supply voltage level different from a second power supply voltage level of the second power domain.
Dependencies are inferred from the claim text.