Electrostatic protection circuit and semiconductor device including the same

A semiconductor device, comprising:

• an output driver including a pull-up driver electrically connected between a first terminal and a second terminal and configured to respond to pull-up data, and a pull-down driver electrically connected between the first terminal and a third terminal and configured to respond to pull-down data;
• and
• an electrostatic protection circuit including,
• a first diode including an anode electrically connected to the first terminal and a cathode electrically connected to the second terminal,
• a second diode including an anode electrically connected to the third terminal and a cathode electrically connected to the first terminal,
• a resistor electrically connected between the second terminal and a first node,
• a capacitor electrically connected between the first node and the third terminal,
• an inverter electrically connected between the first node and a second node, the inverter configured to invert a signal of the first node to generate an inverted signal, and to provide the inverted signal to the second node,
• a gate-coupled transistor electrically connected between the second terminal and the third terminal, the gate-coupled transistor including a gate electrically connected to the second node such that the gate-coupled transistor is configured to respond to the inverted signal of the second node,
• a first switch electrically connected between a substrate of the pull-up driver and the second terminal, the first switch configured to block a first leakage current from flowing from the first terminal to the second terminal through the substrate of the pull-up driver, in response to the inverted signal of the second node, and
• a second switch electrically connected between a substrate of the pull-down driver and the third terminal, the second switch configured to block a second leakage current from flowing from the first terminal to the third terminal through the substrate of the pull-down driver, in response to the signal of the first node.

A semiconductor memory device comprising:

• a command and address generator configured to,
• generate an active command, a read command, and an impedance adjustment command by decoding an inversion chip selection signal and a command signal included in a command/address signal in response to a clock signal,
• generate a row address based on an address signal included in the command/address signal, in response to the active command, and
• generate a column address based on the address signal, in response to the read command;
• a row decoder configured to generate word line selection signals by decoding the row address;
• a column decoder configured to generate column selection signals by decoding the column address;
• a memory cell array configured to output data from a plurality of memory cells selected in response to the word line selection signals and the column selection signals;
• a data read path unit configured to input the data, and to generate read data;
• a pre-driver configured to generate bits of pull-up data or pull-down data, in response to the read data;
• and
• a circuit electrically connected between a power voltage terminal and a ground voltage terminal and configured to, when the read command is generated, generate output data to a data terminal in response to the bits of the pull-up data or the pull-down data, and configured to, when static electricity is applied, perform an electrostatic discharge operation, the circuit including,
• a main driver including a pull-up driver electrically connected between the data terminal and the power voltage terminal, and a pull-down driver electrically connected between the data terminal and the ground voltage terminal;
• and
• an electrostatic protection circuit including:
• a first diode including an anode electrically connected to the data terminal and a cathode electrically connected to the power voltage terminal,
• a second diode including an anode electrically connected to the ground voltage terminal and a cathode electrically connected to the data terminal,
• a resistor electrically connected between the power voltage terminal and a first node,
• a capacitor electrically connected between the first node and the ground voltage terminal,
• an inverter electrically connected between the first node and a second node, the inverter configured to invert a signal of the first node to generate an inverted signal, and to provide the inverted signal to the second node,
• a gate-coupled transistor electrically connected between the power voltage terminal and the ground voltage terminal, the gate-coupled transistor including a gate electrically connected to the second node such that the gate-coupled transistor is configured to respond to the inverted signal of the second node,
• a first switch electrically connected between a substrate of the pull-up driver and the power voltage terminal, the first switch configured to block a first leakage current from flowing from the data terminal to the power voltage terminal through the substrate of the pull-up driver, in response to the inverted signal of the second node, and
• a second switch electrically connected between a substrate of the pull-down driver and the ground voltage terminal, the second switch configured to block a second leakage current from flowing from the data terminal to the ground voltage terminal through the substrate of the pull-down driver, in response to the signal of the first node.