Variable resistance memory device

A variable resistance memory device, comprising:

• a plurality of first conductive lines that extend in a first direction;
• a plurality of second conductive lines that extend in a second direction crossing the first direction and are arranged on the plurality of first conductive lines;
• a plurality of first cell structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first cell structures including a switching pattern and a variable resistance pattern;
• and
• a plurality of first buried structures that fill a plurality of first trenches between the plurality of first conductive lines and extend in the first direction,
• wherein each of the plurality of first buried structures includes:
• a first liner pattern that covers sidewalls of a corresponding first trench of the plurality of first trenches;
• a first filling pattern on the first liner pattern and in the corresponding first trench;
• and
• a capping pattern disposed in the corresponding first trench,
• wherein the capping pattern covers a top surface of the first liner pattern and a top surface of the first filling pattern,
• wherein a bottom surface of the capping pattern has a convex shape toward the capping pattern,
• wherein the lowermost bottom surface of the capping pattern is positioned at a level that is equal to or greater than about ⅔ times a height of a first conductive line of the plurality of first conductive lines, and
• wherein the first conductive line is adjacent to the corresponding first trench.

A variable resistance memory device, comprising:

• a substrate;
• a plurality of first conductive lines on the substrate, the plurality of first conductive lines extending in a first direction;
• a plurality of second conductive lines that extend in a second direction crossing the first direction and are arranged on the plurality of first conductive lines;
• a plurality of first cell structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines;
• a plurality of first buried structures that fill a plurality of first trenches between the plurality of first conductive lines and extend in the first direction;
• and
• a plurality of second buried structures that fill a plurality of second trenches between the plurality of first cell structures,
• wherein each of the plurality of first buried structures includes:
• a first liner pattern that covers sidewalls of a corresponding first trench among the plurality of first trenches;
• a first filling pattern on the first liner pattern and in the corresponding first trench;
• and
• a first capping pattern on the first filling pattern and in the corresponding first trench,
• wherein each of the plurality of second buried structures includes a second liner pattern and a second filling pattern,
• wherein each of the first plurality of cell structures includes a first electrode, a switching pattern, a second electrode, a variable resistance pattern, and a third electrode that are sequentially provided, and
• wherein the plurality of second buried structures extend in the plurality of second trenches and are connected with a plurality of first capping patterns of the plurality of first buried structures.