Fin-based laterally diffused structure having a gate with two adjacent metal layers and method for manufacturing the same

A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:

• a first source/drain region and a second source/drain region in a semiconductor fin;
• a trench isolation between the first and second source/drain regions in the semiconductor fin;
• a first doping region about the first source/drain region, the first doping region defining a channel region in the semiconductor fin;
• a second doping region about the second source/drain region, the second doping region defining a drain extension in the semiconductor fin;
• and
• a gate structure over the channel region and the drain extension, the gate structure including:
• a gate dielectric layer,
• a first metal layer adjacent a second metal layer over the gate dielectric layer wherein the first metal layer and the second metal layer have different thicknesses, and
• a contiguous gate conductor over the first metal layer and the second metal layer,
• wherein a sidewall of the trench isolation is substantially aligned with a sidewall of the second metal layer, and an uppermost surface of the trench isolation is substantially coplanar with a surface of the gate dielectric layer under the first metal layer.

A method, comprising:

• forming a first doping region about a first source/drain region in a semiconductor fin, and a second doping region about a second source/drain region in the semiconductor fin, the first doping region defining a channel region in the semiconductor fin, the second doping region defining a drain extension in the semiconductor fin;
• forming a gate dielectric layer over the channel region and the drain extension;
• forming a first metal layer adjacent a second metal layer over the gate dielectric layer wherein the first metal layer and the second metal layer have different thicknesses;
• forming a contiguous gate conductor over the first metal layer and the second metal layer;
• and
• forming a trench isolation between the first and second source/drain regions in the semiconductor fin, wherein a sidewall of the trench isolation is substantially aligned with a sidewall of the second metal layer,
• wherein forming the gate dielectric layer includes forming the gate dielectric layer with a uniform thickness over the channel region and the drain extension, and forming the first and second metal layers includes forming the first metal layer thinner than the second metal layer.