Transistor structure and manufacturing method of the same

A transistor structure, comprising:

• a substrate, comprising an N+ buried layer;
• a first gate stripe extending along a longitudinal direction over the substrate;
• a second gate stripe over the substrate, separated from the first gate stripe by a predetermined distance;
• a continuous sidewall spacer between the first gate stripe and the second gate stripe, the continuous sidewall spacer is in direct contact with both the first gate stripe and the second gate stripe, wherein the continuous sidewall spacer has a first spacer length along the longitudinal direction and a first spacer width along a horizontal direction orthogonal to the longitudinal direction, the first spacer length is greater than the first spacer width, the continuous sidewall spacer comprises a dimple recess, wherein the predetermined distance is greater than an entire width of the second gate stripe along the horizontal direction;
• a first un-merged sidewall spacer at a side of the first gate stripe opposite to a side of the continuous sidewall spacer;
• a source region in the substrate and aligned to a sidewall of the first un-merged sidewall spacer;
• a drain region in the substrate, the drain region is apart from the source region;
• a lightly doped region in the substrate and aligned to a sidewall of the first gate stripe;
• a P-type well of the substrate surrounding the source region;
• and
• an N-type well of the substrate surrounding the drain region, a boundary of the P-type well and the N-type well is under the first gate stripe, the N-type well has a N-well length along the longitudinal direction, the continuous sidewall spacer is entirely within a vertical projection area of the N-type well from top view perspective, wherein the first un-merged sidewall spacer is entirely within a vertical projection area of the P-type well, the first un-merged sidewall spacer is free from overlapping with the N-type well from top view, and the second gate stripe is entirely within a vertical projection area of the N-type well;
• wherein a bottom surface of the P-type well and a bottom surface of the N-type well are substantially at a same depth from the first gate stripe, the drain length is identical with the first spacer length, the drain length is less than the N-well length, wherein
• the first spacer width is measured from one side of the continuous sidewall spacer to an opposite side of the continuous sidewall spacer across the longitudinal direction;
• the drain length is measured from one edge of the drain region to an opposite edge of the drain region along the longitudinal direction;
• and
• the N-well length is measured from one side of the N-type well to an opposite side of the N-type well across the longitudinal direction.

A transistor structure, comprising:

• a substrate;
• a first gate extending along a longitudinal direction over the substrate, the first gate comprising a gate electrode, wherein the first gate has a first length along the longitudinal direction;
• a second gate over the substrate and laterally in contact with the first gate, wherein the second gate has a second length along the longitudinal direction and a second width along a horizontal direction orthogonal to the longitudinal direction, wherein the second length is greater than the second width, and the second length substantially equals the first length;
• a source region of a first conductivity type in the substrate, aligning to an edge in proximity to a side of the first gate, having a source length substantially equals the first length;
• a P-type well surrounding the source region;
• a drain region of the first conductivity type in the substrate, aligning to an edge in proximity to a side of the second gate, and having a drain length substantially equals the first length;
• an N-type well surrounding the drain region, wherein the N-type well has an N-well length along the longitudinal direction, the N-well length is greater than the second length of the second gate, the second gate is entirely within a vertical projection area of the N-type well, a sidewall of the N-type well directly contacts a sidewall of the P-type well, and a bottom surface of the P-type well and a bottom surface of the N-type well are substantially at a same depth from the first gate;
• a lightly doped region in the P-type well, aligning to a sidewall of the gate electrode of the first gate, wherein a boundary between the P-type well and the N-type well is under the first gate;
• and
• a continuous sidewall spacer between the first gate and the second gate, wherein the continuous sidewall spacer has a continuous sidewall spacer length along the longitudinal direction and a continuous sidewall spacer width along the horizontal direction, the continuous sidewall spacer length is measured from one side of the continuous sidewall spacer to an opposite side of the continuous sidewall spacer across the longitudinal direction, the continuous sidewall spacer width is measured from one edge of the continuous sidewall spacer to an opposite edge of the continuous sidewall spacer across the horizontal direction, the continuous sidewall spacer length is greater than the continuous sidewall spacer width, wherein:
• the drain length is measured from one edge of the drain region to an opposite edge of the drain region along the longitudinal direction;
• the source length is measured from one edge of the source region to an opposite edge of the source region along the longitudinal direction;
• the second length is measured from one side of the second gate to an opposite side of the second gate across the longitudinal direction;
• the second width is measured from one edge of the second gate to an opposite edge of the second gate across the horizontal direction;
• and
• the N-well length is measured from one side of the N-type well to an opposite side of the N-type well across the longitudinal direction.