Multi-height finfet device by selective oxidation

A method comprising:

• forming a non-planar conducting channel of a multi-gate device on a substrate;
• forming a layer of a catalyst material on the channel, wherein the catalyst material comprises a material having a property that enhances oxidation of a material of the channel, the catalyst material comprising aluminum oxide;
• oxidizing a portion of the channel to form an insulator portion of the channel, the insulator portion defined by a height dimension of the channel measured from a surface of the substrate that is less than an overall height dimension of the channel, wherein the insulator portion of the channel is an oxidized portion of a same semiconductor material as the semiconductor material of the non-oxidized portion of the channel, and the insulator portion of the channel has a top surface, wherein the channel is disposed between junction regions on the substrate, wherein the junction region on each of opposite sides of the channel has a bottom surface below a bottom surface of a conducting portion of the channel, and wherein there is no oxide material beneath and in contact with the bottom surface of the junction region on each of opposite sides of the channel;
• forming a gate stack on the channel, the gate stack comprising a dielectric material and a gate electrode, wherein the gate stack has a bottom surface co-planar with the top surface of the insulator portion of the channel;
• and
• forming a second gate stack on a second channel of a second multi-gate device on the substrate, wherein the second channel does not include an insulator portion, wherein the second channel of the second multi-gate device has a bottommost surface above a bottommost surface of the insulator portion of the channel of the multi-gate device, and wherein the non-oxidized portion of the channel of the multi-gate device has a vertical length less than a vertical length of the second channel of the second multi-gate device.

An apparatus comprising:

• a non-planar multi-gate device on a substrate comprising a channel comprising a height dimension defining a conducting portion and an insulator portion, and a gate stack disposed on the channel, wherein the insulator portion of the channel is an oxidized portion of a same semiconductor material as the semiconductor material of the non-oxidized portion of the channel, and the insulator portion of the channel has a top surface, the gate stack comprising a dielectric material and a gate electrode, wherein the gate stack has a bottom surface co-planar with the top surface of the insulator portion of the channel, wherein the multi-gate device further comprises a junction region on each of opposite sides of the channel, wherein the junction region on each of opposite sides of the channel has a bottom surface below a bottom surface of the conducting portion of the channel, and wherein there is no oxide material beneath and in contact with the bottom surface of the junction region on each of opposite sides of the channel;
• and
• a second non-planar multi-gate device on the substrate, the second non-planar multi-gate device comprising a second gate stack on a second channel, wherein the second channel does not include an insulator portion, wherein the second channel of the second non-planar multi-gate device has a bottommost surface above a bottommost surface of the insulator portion of the channel of the non-planar multi-gate device, and wherein the non-oxidized portion of the channel of the multi-gate device has a vertical length less than a vertical length of the second channel of the second multi-gate device.