Memory transistor with multiple charge storing layers and a high work function gate electrode
AssigneeLongitude Flash Memory Solutions Ltd.
InventorsIgor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
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Abstract
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
Claims45
A method comprising:
- forming over a substrate a stack of layers including at least a first dielectric layer, a sacrificial layer and a second dielectric layer, wherein the sacrificial layer is separated from the substrate by the first dielectric layer and the second dielectric layer is separated from the first dielectric layer by the sacrificial layer;
- forming an opening extending through the stack of layers to a first doped diffusion region formed on the substrate;
- forming on sidewalls of the opening a blocking dielectric layer;
- forming on an inside sidewall of the blocking dielectric layer a multi-layer charge storing region;
- forming on an inside sidewall of the multi-layer charge storing region a tunnel dielectric layer;
- and
- forming on an inside sidewall of the tunnel dielectric layer a vertical channel having a semiconductor material extending from the first doped diffusion region through the opening to a top of the stack of layers.
A method comprising:
- forming over a substrate a stack of layers including at least a first dielectric layer, a sacrificial layer and a second dielectric layer, wherein the sacrificial layer is separated from the substrate by the first dielectric layer and the second dielectric layer is separated from the first dielectric layer by the sacrificial layer;
- forming an opening extending through the stack of layers towards the substrate;
- forming on sidewalls of the opening an annular shaped blocking dielectric layer;
- forming on an inside sidewall of the blocking dielectric layer an annular shaped multi-layer charge storing region;
- forming on an inside sidewall of the multi-layer charge storing region an annular shaped tunnel dielectric layer;
- and
- forming on an inside sidewall of the tunnel dielectric layer an annular shaped vertical channel having a semiconductor material extending from the substrate through the opening towards a top of the stack of layers.
A semiconductor memory device, comprising:
- a semiconductor substrate,
- a channel region oriented substantially perpendicular to the semiconductor substrate, the channel region formed in a substantially annular shape,
- a tunnel dielectric layer surrounding the channel region, the tunnel dielectric layer formed in a substantially annular shape,
- a multi-layer charge storing region surrounding the tunnel dielectric layer, the multi-layer charge storing region formed in a substantially annular shape,
- a blocking dielectric layer surrounding the multi-layer charge storing region, the blocking dielectric layer formed in a substantially annular shape, and
- a gate electrode surrounding the blocking dielectric layer.
Dependencies are inferred from the claim text.