Bulk nanosheet with dielectric isolation

A method of forming a device structure with dielectric isolation, the method comprising:

• forming a plurality of nanosheets of alternating material layers as a stack on a bulk semiconductor wafer, a bottom nanosheet material layer of the stack comprising Si and Ge;
• etching through the plurality of nanosheets to form (i) two or more nanowire stacks on the bulk semiconductor wafer and (ii) one or more trenches between the two or more nanowire stacks such that a bottom surface of each of the one or more trenches is substantially coplanar with an interface between (i) the bulk semiconductor wafer and (ii) a bottom nanowire comprising Si and Ge;
• subsequent to etching through the plurality of nanosheets, forming spacers covering sidewalls of the two or more nanowire stacks;
• and
• oxidizing a top portion of the bulk semiconductor wafer through each of the one or more trenches, wherein the oxidizing forms a dielectric isolation region in the top portion of the bulk semiconductor wafer.