Memory device

A memory device comprising:

• a peripheral circuit region comprising a peripheral circuit structure and a first metal pad;
• and
• a cell region comprising a substrate, a plurality of upper interconnection layers in the substrate, a cell array structure on the substrate, a common source line interposed between the substrate and the cell array structure, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad,
• wherein the cell array structure comprises:
• a memory stack including a memory cell region and a connection stepped region located at one side of the memory cell region, the memory cell region having a plurality of gate lines;
• and
• a word line cut region extending across the plurality of gate lines and extending through a through hole of the common source line to be connected to a first upper interconnection layer pattern from among the plurality of upper interconnection layers, the first upper interconnection layer pattern being a floating conductive interconnection layer pattern spaced apart from other upper interconnection layer patterns from among the plurality of upper interconnection layers.

A memory device comprising:

• a peripheral circuit region comprising a first substrate, a plurality of peripheral circuit conductive interconnection layers formed on the first substrate, and a first metal pad;
• a cell region comprising a second substrate, a plurality of upper interconnection layers in the second substrate, a cell array structure comprising a plurality of gate lines on the second substrate, a common source line interposed between the second substrate and the cell array structure, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad;
• and
• a word line cut region comprising a first portion and a second portion, the first portion extending lengthwise in a lateral direction across the plurality of gate lines and a through hole, the second portion being integrally connected to the first portion and extending through a portion of the second substrate to a first upper interconnection layer pattern from among the plurality of upper interconnection layers.