Semiconductor device having word line separation layer

A semiconductor device comprising:

• a substrate including a cell array area and first and second connecting areas disposed at opposite sides of the cell array area, each of the first and second connecting areas including a plurality of through-silicon-via (TSV) areas;
• a peripheral circuit structure disposed on the substrate;
• a lower stack disposed in the peripheral circuit structure and an upper stack disposed on the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers;
• a plurality of channel structures extending through the lower stack and the upper stack in the cell array area;
• a plurality of dummy channel structures extending through the lower stack and the upper stack in the connecting areas;
• a plurality of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a first direction, the separation insulating layers being spaced apart from one another in a second direction crossing the first direction;
• and
• a plurality of word line separation layers disposed at an upper portion of the lower stack and crossing two adjacent separation insulating layers among the plurality of separation insulating layers, the plurality of word line separation layers extending vertically through at least one of the lower word lines,
• wherein the plurality of word line separation layers include first word line separation layers arranged into a first column in the first connecting area and second word line separation layers arranged into a second column in the second connecting area, the first word line separation layers and the second word line separation layers are arranged into a zigzag manner in the second direction.

A semiconductor device comprising:

• a substrate including a cell array area and a connecting area, the connecting area including a through-silicon-via (TSV) area;
• a peripheral circuit structure disposed on the substrate;
• a lower conductive layer disposed on the peripheral circuit structure;
• a connecting conductive layer disposed on the lower conductive layer in the cell array area;
• a connecting mold layer disposed on the lower conductive layer in the connecting area;
• a supporter disposed on the connecting conductive layer and the connecting mold layer;
• a buried insulating layer disposed in the TSV area and extending through the lower conductive layer, the connecting mold layer and the supporter;
• a lower stack disposed on the supporter, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers;
• an upper stack disposed on the lower stack, the upper stack including a plurality of upper insulating layers and a plurality of upper word lines alternately stacked with the upper insulating layers;
• a plurality of channel structures extending through the lower stack and the upper stack in the cell array area;
• a plurality of dummy channel structures extending through the lower stack and the upper stack in the connecting area;
• a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a first horizontal direction, the pair of separation insulating layers being spaced apart from each other in a second horizontal direction crossing the first horizontal direction;
• a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers, the word line separation layer extending vertically through at least one of the lower word lines and extending in the second horizontal direction;
• and
• a TSV disposed in the TSV area, the TSV extending through the upper stack and the lower stack and connected to the peripheral circuit structure, wherein the lower stack further includes a plurality of lower sacrificial layers disposed at the same level as the plurality of lower word lines in the TSV area;
• wherein the TSV extends vertically through the plurality of lower sacrificial layers, and
• wherein a lower surface of the word line separation layer is disposed at a higher level than a lower surface of the lower stack.