Low-voltage flash memory integrated with a vertical field effect transistor

A semiconductor structure comprising:

• a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element, the low-voltage flash memory is coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines,
• wherein the low-voltage flash memory comprises:
• a first source drain region;
• a second source drain region, the second source drain region separated from the first source drain region by an epitaxial channel;
• a floating gate, the floating gate separated from the epitaxial channel by a first dielectric layer wherein the floating gate has a doping type that is opposite to a doping type of the epitaxial channel;
• and
• a control gate, the control gate separated from the floating gate by a second dielectric Previously Presented.

A semiconductor structure comprising:

• a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element, the low-voltage flash memory is coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines,
• wherein the low-voltage flash memory comprises:
• a first source drain region;
• a second source drain region, the second source drain region separated from the first source drain region by an epitaxial channel;
• a floating gate, the floating gate separated from the epitaxial channel by a first dielectric layer, wherein the first dielectric is made of high-k dielectric material;
• and
• a control gate, the control gate separated from the floating gate by a second dielectric layer.

A method comprising:

• forming a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element, the low-voltage flash memory is coupled to the non-volatile memory element by the vertical field effect transistor, wherein forming the low-voltage flash memory comprises:
• growing a first source drain region on a substrate;
• epitaxially growing an epitaxial channel on the first source drain region;
• epitaxially growing a second source drain region on the epitaxial channel;
• forming a floating gate around the epitaxial channel, wherein the floating gate has a doping type that is opposite to a doping type of the epitaxial channel;
• and
• forming a control gate around the floating gate, the control gate being separated from the floating gate by a first dielectric layer.